From ee62a0fec8e63f45f816c61ab9fb28aba7414185 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Mon, 11 Aug 2008 12:22:16 -0700 Subject: params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end. --- src/cpu/o3/cpu.hh | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 61d7dcf22..611d03bad 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -53,6 +53,8 @@ //#include "cpu/o3/thread_context.hh" #include "sim/process.hh" +#include "params/DerivO3CPU.hh" + template class Checker; class ThreadContext; @@ -63,13 +65,13 @@ class Checkpoint; class MemObject; class Process; +class BaseCPUParams; + class BaseO3CPU : public BaseCPU { //Stuff that's pretty ISA independent will go here. public: - typedef BaseCPU::Params Params; - - BaseO3CPU(Params *params); + BaseO3CPU(BaseCPUParams *params); void regStats(); @@ -96,7 +98,6 @@ class FullO3CPU : public BaseO3CPU typedef typename Impl::CPUPol CPUPolicy; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::O3CPU O3CPU; - typedef typename Impl::Params Params; typedef O3ThreadState Thread; @@ -256,7 +257,7 @@ class FullO3CPU : public BaseO3CPU public: /** Constructs a CPU with the given parameters. */ - FullO3CPU(O3CPU *o3_cpu, Params *params); + FullO3CPU(O3CPU *o3_cpu, DerivO3CPUParams *params); /** Destructor. */ ~FullO3CPU(); -- cgit v1.2.3 From e09c403d326488dbc709e3bddc8d497481273950 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 9 Oct 2008 00:08:50 -0700 Subject: O3: Generalize the O3 CPU object so it isn't split out by ISA. --- src/cpu/o3/cpu.hh | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 82 insertions(+), 7 deletions(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 611d03bad..065dd10a0 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -99,6 +99,7 @@ class FullO3CPU : public BaseO3CPU typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::O3CPU O3CPU; + typedef O3ThreadState ImplState; typedef O3ThreadState Thread; typedef typename std::list::iterator ListIt; @@ -201,6 +202,13 @@ class FullO3CPU : public BaseO3CPU activateThreadEvent[tid].squash(); } +#if !FULL_SYSTEM + TheISA::IntReg getSyscallArg(int i, int tid); + + /** Used to shift args for indirect syscall. */ + void setSyscallArg(int i, TheISA::IntReg val, int tid); +#endif + /** The tick event used for scheduling CPU ticks. */ ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; @@ -257,12 +265,12 @@ class FullO3CPU : public BaseO3CPU public: /** Constructs a CPU with the given parameters. */ - FullO3CPU(O3CPU *o3_cpu, DerivO3CPUParams *params); + FullO3CPU(DerivO3CPUParams *params); /** Destructor. */ ~FullO3CPU(); /** Registers statistics. */ - void fullCPURegStats(); + void regStats(); void demapPage(Addr vaddr, uint64_t asn) { @@ -368,12 +376,16 @@ class FullO3CPU : public BaseO3CPU virtual void unserialize(Checkpoint *cp, const std::string §ion); public: - /** Executes a syscall on this cycle. - * --------------------------------------- - * Note: this is a virtual function. CPU-Specific - * functionality defined in derived classes +#if !FULL_SYSTEM + /** Executes a syscall. + * @todo: Determine if this needs to be virtual. */ - virtual void syscall(int tid) { panic("Unimplemented!"); } + void syscall(int64_t callnum, int tid); + + /** Sets the return value of a syscall. */ + void setSyscallReturn(SyscallReturn return_value, int tid); + +#endif /** Starts draining the CPU's pipeline of all instructions in * order to stop all memory accesses. */ @@ -395,7 +407,27 @@ class FullO3CPU : public BaseO3CPU InstSeqNum getAndIncrementInstSeq() { return globalSeqNum++; } + /** Traps to handle given fault. */ + void trap(Fault fault, unsigned tid); + #if FULL_SYSTEM + /** Posts an interrupt. */ + void post_interrupt(int int_num, int index); + + /** HW return from error interrupt. */ + Fault hwrei(unsigned tid); + + bool simPalCheck(int palFunc, unsigned tid); + + /** Returns the Fault for any valid interrupt. */ + Fault getInterrupts(); + + /** Processes any an interrupt fault. */ + void processInterrupts(Fault interrupt); + + /** Halts the CPU. */ + void halt() { panic("Halt not implemented!\n"); } + /** Update the Virt and Phys ports of all ThreadContexts to * reflect change in memory connections. */ void updateMemPorts(); @@ -425,6 +457,24 @@ class FullO3CPU : public BaseO3CPU #endif /** Register accessors. Index refers to the physical register index. */ + + /** Reads a miscellaneous register. */ + TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid); + + /** Reads a misc. register, including any side effects the read + * might have as defined by the architecture. + */ + TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid); + + /** Sets a miscellaneous register. */ + void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid); + + /** Sets a misc. register, including any side effects the write + * might have as defined by the architecture. + */ + void setMiscReg(int misc_reg, const TheISA::MiscReg &val, + unsigned tid); + uint64_t readIntReg(int reg_idx); TheISA::FloatReg readFloatReg(int reg_idx); @@ -496,6 +546,12 @@ class FullO3CPU : public BaseO3CPU /** Sets the commit next micro PC of a specific thread. */ void setNextMicroPC(Addr val, unsigned tid); + /** Initiates a squash of all in-flight instructions for a given + * thread. The source of the squash is an external update of + * state through the TC. + */ + void squashFromTC(unsigned tid); + /** Function to add instruction onto the head of the list of the * instructions. Used when new instructions are fetched. */ @@ -711,6 +767,25 @@ class FullO3CPU : public BaseO3CPU /** Available thread ids in the cpu*/ std::vector tids; + /** CPU read function, forwards read to LSQ. */ + template + Fault read(RequestPtr &req, T &data, int load_idx) + { + return this->iew.ldstQueue.read(req, data, load_idx); + } + + /** CPU write function, forwards write to LSQ. */ + template + Fault write(RequestPtr &req, T &data, int store_idx) + { + return this->iew.ldstQueue.write(req, data, store_idx); + } + + Addr lockAddr; + + /** Temporary fix for the lock flag, works in the UP case. */ + bool lockFlag; + /** Stat for total number of times the CPU is descheduled. */ Stats::Scalar<> timesIdled; /** Stat for total number of cycles the CPU spends descheduled. */ -- cgit v1.2.3 From e06321091d4e931ff1a4d753e56d76f9746c3cd2 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 9 Oct 2008 04:58:24 -0700 Subject: eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5. --- src/cpu/o3/cpu.hh | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 065dd10a0..406d965be 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -148,9 +148,9 @@ class FullO3CPU : public BaseO3CPU void scheduleTickEvent(int delay) { if (tickEvent.squashed()) - tickEvent.reschedule(nextCycle(curTick + ticks(delay))); + reschedule(tickEvent, nextCycle(curTick + ticks(delay))); else if (!tickEvent.scheduled()) - tickEvent.schedule(nextCycle(curTick + ticks(delay))); + schedule(tickEvent, nextCycle(curTick + ticks(delay))); } /** Unschedule tick event, regardless of its current state. */ @@ -188,11 +188,11 @@ class FullO3CPU : public BaseO3CPU { // Schedule thread to activate, regardless of its current state. if (activateThreadEvent[tid].squashed()) - activateThreadEvent[tid]. - reschedule(nextCycle(curTick + ticks(delay))); + reschedule(activateThreadEvent[tid], + nextCycle(curTick + ticks(delay))); else if (!activateThreadEvent[tid].scheduled()) - activateThreadEvent[tid]. - schedule(nextCycle(curTick + ticks(delay))); + schedule(activateThreadEvent[tid], + nextCycle(curTick + ticks(delay))); } /** Unschedule actiavte thread event, regardless of its current state. */ @@ -246,11 +246,11 @@ class FullO3CPU : public BaseO3CPU { // Schedule thread to activate, regardless of its current state. if (deallocateContextEvent[tid].squashed()) - deallocateContextEvent[tid]. - reschedule(nextCycle(curTick + ticks(delay))); + reschedule(deallocateContextEvent[tid], + nextCycle(curTick + ticks(delay))); else if (!deallocateContextEvent[tid].scheduled()) - deallocateContextEvent[tid]. - schedule(nextCycle(curTick + ticks(delay))); + schedule(deallocateContextEvent[tid], + nextCycle(curTick + ticks(delay))); } /** Unschedule thread deallocation in CPU */ -- cgit v1.2.3 From da7209ec93f3cdad11c02906357f06fa29652996 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 11 Oct 2008 02:27:21 -0700 Subject: CPU: Eliminate the hwrei function. --- src/cpu/o3/cpu.hh | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 406d965be..cdc1d2e58 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -414,9 +414,6 @@ class FullO3CPU : public BaseO3CPU /** Posts an interrupt. */ void post_interrupt(int int_num, int index); - /** HW return from error interrupt. */ - Fault hwrei(unsigned tid); - bool simPalCheck(int palFunc, unsigned tid); /** Returns the Fault for any valid interrupt. */ -- cgit v1.2.3 From f621b7b81f0913612381d5dc4993f52bb2116902 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sat, 11 Oct 2008 12:17:24 -0700 Subject: CPU: Eliminate the simPalCheck funciton. --- src/cpu/o3/cpu.hh | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index cdc1d2e58..07ba8d701 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -414,8 +414,6 @@ class FullO3CPU : public BaseO3CPU /** Posts an interrupt. */ void post_interrupt(int int_num, int index); - bool simPalCheck(int palFunc, unsigned tid); - /** Returns the Fault for any valid interrupt. */ Fault getInterrupts(); -- cgit v1.2.3 From b760b99f4d9f5469d88c67ae8a06e5f9543a43e7 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Mon, 20 Oct 2008 16:22:59 -0400 Subject: O3CPU: Undo Gabe's changes to remove hwrei and simpalcheck from O3 CPU. Removing hwrei causes the instruction after the hwrei to be fetched before the ITB/DTB_CM register is updated in a call pal call sys and thus the translation fails because the user is attempting to access a super page address. Minimally, it seems as though some sort of fetch stall or refetch after a hwrei is required. I think this works currently because the hwrei uses the exec context interface, and the o3 stalls when that occurs. Additionally, these changes don't update the LOCK register and probably break ll/sc. Both o3 changes were removed since a great deal of manual patching would be required to only remove the hwrei change. --- src/cpu/o3/cpu.hh | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 07ba8d701..406d965be 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -414,6 +414,11 @@ class FullO3CPU : public BaseO3CPU /** Posts an interrupt. */ void post_interrupt(int int_num, int index); + /** HW return from error interrupt. */ + Fault hwrei(unsigned tid); + + bool simPalCheck(int palFunc, unsigned tid); + /** Returns the Fault for any valid interrupt. */ Fault getInterrupts(); -- cgit v1.2.3 From 9836d81c2bba97e36c43ca22feee1d51a12ce6ac Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Tue, 21 Oct 2008 07:12:53 -0700 Subject: style: Use the correct m5 style for things relating to interrupts. --- src/cpu/o3/cpu.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 406d965be..8cfc9affa 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -412,7 +412,7 @@ class FullO3CPU : public BaseO3CPU #if FULL_SYSTEM /** Posts an interrupt. */ - void post_interrupt(int int_num, int index); + void postInterrupt(int int_num, int index); /** HW return from error interrupt. */ Fault hwrei(unsigned tid); -- cgit v1.2.3 From 8788d703f81cef20916ffd2c7e0d28031cf65df8 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Thu, 23 Oct 2008 16:49:17 -0400 Subject: s/cpu_id/cpuId in o3 (to be consistent and match style), also fix some typos in comments. --- src/cpu/o3/cpu.hh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 8cfc9affa..d1cc8bea5 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -76,13 +76,13 @@ class BaseO3CPU : public BaseCPU void regStats(); /** Sets this CPU's ID. */ - void setCpuId(int id) { cpu_id = id; } + void setCpuId(int id) { cpuId = id; } /** Reads this CPU's ID. */ - int readCpuId() { return cpu_id; } + int readCpuId() { return cpuId; } protected: - int cpu_id; + int cpuId; }; /** -- cgit v1.2.3 From c55a467a06eaa59c47c52a2adddc266b8e545589 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Sun, 2 Nov 2008 21:56:57 -0500 Subject: make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. --- src/cpu/o3/cpu.hh | 9 --------- 1 file changed, 9 deletions(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index d1cc8bea5..c60c20d55 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -74,15 +74,6 @@ class BaseO3CPU : public BaseCPU BaseO3CPU(BaseCPUParams *params); void regStats(); - - /** Sets this CPU's ID. */ - void setCpuId(int id) { cpuId = id; } - - /** Reads this CPU's ID. */ - int readCpuId() { return cpuId; } - - protected: - int cpuId; }; /** -- cgit v1.2.3 From 1adfe5c7f3368c4225ff685ddcd66b6280c7599f Mon Sep 17 00:00:00 2001 From: Clint Smullen Date: Mon, 10 Nov 2008 11:51:18 -0800 Subject: O3CPU: Make the instcount debugging stuff per-cpu. This is to prevent the assertion from firing if you have a large multicore. Also make sure that it's not compiled in when NDEBUG is defined --- src/cpu/o3/cpu.hh | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index c60c20d55..d24e8c383 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -576,6 +576,11 @@ class FullO3CPU : public BaseO3CPU void dumpInsts(); public: +#ifndef NDEBUG + /** Count of total number of dynamic instructions in flight. */ + int instcount; +#endif + /** List of all the instructions in flight. */ std::list instList; -- cgit v1.2.3 From f0fb3ac060234ed5860c8d5bca3e84dbd8d30c36 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Sat, 24 Jan 2009 07:27:21 -0800 Subject: cpu: provide a wakeup mechanism that can be used to pull CPUs out of sleep. Make interrupts use the new wakeup method, and pull all of the interrupt stuff into the cpu base class so that only the wakeup code needs to be updated. I tried to make wakeup, wakeCPU, and the various other mechanisms for waking and sleeping a little more sane, but I couldn't understand why the statistics were changing the way they were. Maybe we'll try again some day. --- src/cpu/o3/cpu.hh | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index d24e8c383..d14001d0d 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -402,9 +402,6 @@ class FullO3CPU : public BaseO3CPU void trap(Fault fault, unsigned tid); #if FULL_SYSTEM - /** Posts an interrupt. */ - void postInterrupt(int int_num, int index); - /** HW return from error interrupt. */ Fault hwrei(unsigned tid); @@ -701,6 +698,10 @@ class FullO3CPU : public BaseO3CPU /** Wakes the CPU, rescheduling the CPU if it's not already active. */ void wakeCPU(); +#if FULL_SYSTEM + virtual void wakeup(); +#endif + /** Gets a free thread id. Use if thread ids change across system. */ int getFreeTid(); -- cgit v1.2.3 From a1aba01a02a8c1261120de83d8fbfd6624f0cb17 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 25 Feb 2009 10:15:34 -0800 Subject: CPU: Get rid of translate... functions from various interface classes. --- src/cpu/o3/cpu.hh | 18 ------------------ 1 file changed, 18 deletions(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index d14001d0d..683e4284f 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -279,24 +279,6 @@ class FullO3CPU : public BaseO3CPU this->dtb->demapPage(vaddr, asn); } - /** Translates instruction requestion. */ - Fault translateInstReq(RequestPtr &req, Thread *thread) - { - return this->itb->translate(req, thread->getTC()); - } - - /** Translates data read request. */ - Fault translateDataReadReq(RequestPtr &req, Thread *thread) - { - return this->dtb->translate(req, thread->getTC(), false); - } - - /** Translates data write request. */ - Fault translateDataWriteReq(RequestPtr &req, Thread *thread) - { - return this->dtb->translate(req, thread->getTC(), true); - } - /** Returns a specific port. */ Port *getPort(const std::string &if_name, int idx); -- cgit v1.2.3 From 9a000c51736d97c1109be296ea7d1fd41d84debb Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 27 Feb 2009 09:22:14 -0800 Subject: Processes: Make getting and setting system call arguments part of a process object. --- src/cpu/o3/cpu.hh | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 683e4284f..f4ed28e8e 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -193,13 +193,6 @@ class FullO3CPU : public BaseO3CPU activateThreadEvent[tid].squash(); } -#if !FULL_SYSTEM - TheISA::IntReg getSyscallArg(int i, int tid); - - /** Used to shift args for indirect syscall. */ - void setSyscallArg(int i, TheISA::IntReg val, int tid); -#endif - /** The tick event used for scheduling CPU ticks. */ ActivateThreadEvent activateThreadEvent[Impl::MaxThreads]; @@ -354,10 +347,6 @@ class FullO3CPU : public BaseO3CPU * @todo: Determine if this needs to be virtual. */ void syscall(int64_t callnum, int tid); - - /** Sets the return value of a syscall. */ - void setSyscallReturn(SyscallReturn return_value, int tid); - #endif /** Starts draining the CPU's pipeline of all instructions in -- cgit v1.2.3 From cc95b5739097e31fdaa36a3ff443861969e338b1 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 5 Mar 2009 19:09:53 -0800 Subject: stats: Fix all stats usages to deal with template fixes --- src/cpu/o3/cpu.hh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'src/cpu/o3/cpu.hh') diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index f4ed28e8e..942970f5f 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -755,13 +755,13 @@ class FullO3CPU : public BaseO3CPU bool lockFlag; /** Stat for total number of times the CPU is descheduled. */ - Stats::Scalar<> timesIdled; + Stats::Scalar timesIdled; /** Stat for total number of cycles the CPU spends descheduled. */ - Stats::Scalar<> idleCycles; + Stats::Scalar idleCycles; /** Stat for the number of committed instructions per thread. */ - Stats::Vector<> committedInsts; + Stats::Vector committedInsts; /** Stat for the total number of committed instructions. */ - Stats::Scalar<> totalCommittedInsts; + Stats::Scalar totalCommittedInsts; /** Stat for the CPI per thread. */ Stats::Formula cpi; /** Stat for the total CPI. */ -- cgit v1.2.3