From e09c403d326488dbc709e3bddc8d497481273950 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 9 Oct 2008 00:08:50 -0700
Subject: O3: Generalize the O3 CPU object so it isn't split out by ISA.

---
 src/cpu/o3/cpu.hh | 89 ++++++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 82 insertions(+), 7 deletions(-)

(limited to 'src/cpu/o3/cpu.hh')

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 611d03bad..065dd10a0 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -99,6 +99,7 @@ class FullO3CPU : public BaseO3CPU
     typedef typename Impl::DynInstPtr DynInstPtr;
     typedef typename Impl::O3CPU O3CPU;
 
+    typedef O3ThreadState<Impl> ImplState;
     typedef O3ThreadState<Impl> Thread;
 
     typedef typename std::list<DynInstPtr>::iterator ListIt;
@@ -201,6 +202,13 @@ class FullO3CPU : public BaseO3CPU
             activateThreadEvent[tid].squash();
     }
 
+#if !FULL_SYSTEM
+    TheISA::IntReg getSyscallArg(int i, int tid);
+
+    /** Used to shift args for indirect syscall. */
+    void setSyscallArg(int i, TheISA::IntReg val, int tid);
+#endif
+
     /** The tick event used for scheduling CPU ticks. */
     ActivateThreadEvent activateThreadEvent[Impl::MaxThreads];
 
@@ -257,12 +265,12 @@ class FullO3CPU : public BaseO3CPU
 
   public:
     /** Constructs a CPU with the given parameters. */
-    FullO3CPU(O3CPU *o3_cpu, DerivO3CPUParams *params);
+    FullO3CPU(DerivO3CPUParams *params);
     /** Destructor. */
     ~FullO3CPU();
 
     /** Registers statistics. */
-    void fullCPURegStats();
+    void regStats();
 
     void demapPage(Addr vaddr, uint64_t asn)
     {
@@ -368,12 +376,16 @@ class FullO3CPU : public BaseO3CPU
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
   public:
-    /** Executes a syscall on this cycle.
-     *  ---------------------------------------
-     *  Note: this is a virtual function. CPU-Specific
-     *  functionality defined in derived classes
+#if !FULL_SYSTEM
+    /** Executes a syscall.
+     * @todo: Determine if this needs to be virtual.
      */
-    virtual void syscall(int tid) { panic("Unimplemented!"); }
+    void syscall(int64_t callnum, int tid);
+
+    /** Sets the return value of a syscall. */
+    void setSyscallReturn(SyscallReturn return_value, int tid);
+
+#endif
 
     /** Starts draining the CPU's pipeline of all instructions in
      * order to stop all memory accesses. */
@@ -395,7 +407,27 @@ class FullO3CPU : public BaseO3CPU
     InstSeqNum getAndIncrementInstSeq()
     { return globalSeqNum++; }
 
+    /** Traps to handle given fault. */
+    void trap(Fault fault, unsigned tid);
+
 #if FULL_SYSTEM
+    /** Posts an interrupt. */
+    void post_interrupt(int int_num, int index);
+
+    /** HW return from error interrupt. */
+    Fault hwrei(unsigned tid);
+
+    bool simPalCheck(int palFunc, unsigned tid);
+
+    /** Returns the Fault for any valid interrupt. */
+    Fault getInterrupts();
+
+    /** Processes any an interrupt fault. */
+    void processInterrupts(Fault interrupt);
+
+    /** Halts the CPU. */
+    void halt() { panic("Halt not implemented!\n"); }
+
     /** Update the Virt and Phys ports of all ThreadContexts to
      * reflect change in memory connections. */
     void updateMemPorts();
@@ -425,6 +457,24 @@ class FullO3CPU : public BaseO3CPU
 #endif
 
     /** Register accessors.  Index refers to the physical register index. */
+
+    /** Reads a miscellaneous register. */
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid);
+
+    /** Reads a misc. register, including any side effects the read
+     * might have as defined by the architecture.
+     */
+    TheISA::MiscReg readMiscReg(int misc_reg, unsigned tid);
+
+    /** Sets a miscellaneous register. */
+    void setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, unsigned tid);
+
+    /** Sets a misc. register, including any side effects the write
+     * might have as defined by the architecture.
+     */
+    void setMiscReg(int misc_reg, const TheISA::MiscReg &val,
+            unsigned tid);
+
     uint64_t readIntReg(int reg_idx);
 
     TheISA::FloatReg readFloatReg(int reg_idx);
@@ -496,6 +546,12 @@ class FullO3CPU : public BaseO3CPU
     /** Sets the commit next micro PC of a specific thread. */
     void setNextMicroPC(Addr val, unsigned tid);
 
+    /** Initiates a squash of all in-flight instructions for a given
+     * thread.  The source of the squash is an external update of
+     * state through the TC.
+     */
+    void squashFromTC(unsigned tid);
+
     /** Function to add instruction onto the head of the list of the
      *  instructions.  Used when new instructions are fetched.
      */
@@ -711,6 +767,25 @@ class FullO3CPU : public BaseO3CPU
     /** Available thread ids in the cpu*/
     std::vector<unsigned> tids;
 
+    /** CPU read function, forwards read to LSQ. */
+    template <class T>
+    Fault read(RequestPtr &req, T &data, int load_idx)
+    {
+        return this->iew.ldstQueue.read(req, data, load_idx);
+    }
+
+    /** CPU write function, forwards write to LSQ. */
+    template <class T>
+    Fault write(RequestPtr &req, T &data, int store_idx)
+    {
+        return this->iew.ldstQueue.write(req, data, store_idx);
+    }
+
+    Addr lockAddr;
+
+    /** Temporary fix for the lock flag, works in the UP case. */
+    bool lockFlag;
+
     /** Stat for total number of times the CPU is descheduled. */
     Stats::Scalar<> timesIdled;
     /** Stat for total number of cycles the CPU spends descheduled. */
-- 
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