From e2507407b17188dca802082434cfe0230d9bfa61 Mon Sep 17 00:00:00 2001 From: Giacomo Gabrielli Date: Fri, 11 Feb 2011 18:29:35 -0600 Subject: O3: Enhance data address translation by supporting hardware page table walkers. Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs, when a TLB miss occurs, initiateTranslation() can return with NoFault but with the translation unfinished. Instructions experiencing a delayed translation due to a hardware page table walk are deferred until the translation completes and kept into the IQ. In order to keep track of them, the IQ has been augmented with a queue of the outstanding delayed memory instructions. When their translation completes, instructions are re-executed (only their initiateAccess() was already executed; their DTB translation is now skipped). The IEW stage has been modified to support such a 2-pass execution. --- src/cpu/o3/fetch.hh | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/cpu/o3/fetch.hh') diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 92691720b..647c48a76 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -136,6 +136,10 @@ class DefaultFetch : fetch(_fetch) {} + void + markDelayed() + {} + void finish(Fault fault, RequestPtr req, ThreadContext *tc, BaseTLB::Mode mode) -- cgit v1.2.3