From 0b3897fc90901953e9d016466c37ab507f85023c Mon Sep 17 00:00:00 2001 From: Anthony Gutierrez Date: Wed, 15 Aug 2012 10:38:08 -0400 Subject: O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs This patch fixes some problems with the drain/switchout functionality for the O3 cpu and for the ARM ISA and adds some useful debug print statements. This is an incremental fix as there are still a few bugs/mem leaks with the switchout code. Particularly when switching from an O3CPU to a TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA I haven't encountered any more assertion failures; now the kernel will typically panic inside of simulation. --- src/cpu/o3/fetch_impl.hh | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/cpu/o3/fetch_impl.hh') diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index b6eb25c08..81d70bd61 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -132,8 +132,10 @@ DefaultFetch::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params) // Get the size of an instruction. instSize = sizeof(TheISA::MachInst); - for (int i = 0; i < Impl::MaxThreads; i++) + for (int i = 0; i < Impl::MaxThreads; i++) { + cacheData[i] = NULL; decoder[i] = new TheISA::Decoder(NULL); + } } template @@ -346,7 +348,8 @@ DefaultFetch::setIcache() for (ThreadID tid = 0; tid < numThreads; tid++) { // Create space to store a cache line. - cacheData[tid] = new uint8_t[cacheBlkSize]; + if (!cacheData[tid]) + cacheData[tid] = new uint8_t[cacheBlkSize]; cacheDataPC[tid] = 0; cacheDataValid[tid] = false; } -- cgit v1.2.3