From cd765c23a2030d45223952315b4e862999714890 Mon Sep 17 00:00:00 2001 From: Nilay Vaish Date: Fri, 10 Feb 2012 08:37:30 -0600 Subject: O3 CPU: Strengthen condition for handling interrupts The condition for handling interrupts is to check whether or not the cpu's instruction list is empty. As observed, this can lead to cases in which even though the instruction list is empty, interrupts are handled when they should not be. The condition is being strengthened so that interrupts get handled only when the last committed microop did not had IsDelayedCommit set. --- src/cpu/o3/fetch_impl.hh | 1 + 1 file changed, 1 insertion(+) (limited to 'src/cpu/o3/fetch_impl.hh') diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 48c21917a..72d9e960e 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1144,6 +1144,7 @@ DefaultFetch::fetch(bool &status_change) // an delayed commit micro-op currently (delayed commit instructions // are not interruptable by interrupts, only faults) ++fetchMiscStallCycles; + DPRINTF(Fetch, "[tid:%i]: Fetch is stalled!\n", tid); return; } } else { -- cgit v1.2.3