From e0de2c34433be76eac7798e58e1ae02f5bffb732 Mon Sep 17 00:00:00 2001
From: Nathan Binkert <nate@binkert.org>
Date: Wed, 8 Apr 2009 22:21:27 -0700
Subject: tlb: More fixing of unified TLB

---
 src/cpu/o3/fetch_impl.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/cpu/o3/fetch_impl.hh')

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index f9cc78c18..fcee2daa6 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -602,7 +602,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid
 
     // Translate the instruction request.
     fault = cpu->itb->translateAtomic(mem_req, cpu->thread[tid]->getTC(),
-            false, true);
+                                      BaseTLB::Execute);
 
     // In the case of faults, the fetch stage may need to stall and wait
     // for the ITB miss to be handled.
-- 
cgit v1.2.3