From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001
From: Yasuko Eckert <yasuko.eckert@amd.com>
Date: Tue, 15 Oct 2013 14:22:44 -0400
Subject: cpu: add a condition-code register class

Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
---
 src/cpu/o3/free_list.cc | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/cpu/o3/free_list.cc')

diff --git a/src/cpu/o3/free_list.cc b/src/cpu/o3/free_list.cc
index 0c8a16d0d..a9544587e 100644
--- a/src/cpu/o3/free_list.cc
+++ b/src/cpu/o3/free_list.cc
@@ -29,7 +29,9 @@
  * Authors: Kevin Lim
  */
 
+#include "arch/registers.hh"
 #include "base/trace.hh"
+#include "config/the_isa.hh"
 #include "cpu/o3/free_list.hh"
 #include "debug/FreeList.hh"
 
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