From 8ade33d324218737c815935120307153975eeadc Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 7 Jul 2006 17:33:24 -0400 Subject: Support Ron's changes for hooking up ports. src/cpu/checker/cpu.hh: Now that BaseCPU is a MemObject, the checker must define this function. src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_unit.hh: Implement getPort function so the connector can connect the ports properly. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: The connector handles connecting the ports now. src/python/m5/objects/O3CPU.py: Add ports to the parameters. --HG-- extra : convert_revision : 0b1a216b9a5d0574e62165d7c6c242498104d918 --- src/cpu/o3/iew.hh | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/cpu/o3/iew.hh') diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index 4908a6649..fb9afde54 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -125,6 +125,9 @@ class DefaultIEW /** Initializes stage; sends back the number of free IQ and LSQ entries. */ void initStage(); + /** Returns the dcache port. */ + Port *getDcachePort() { return ldstQueue.getDcachePort(); } + /** Sets CPU pointer for IEW, IQ, and LSQ. */ void setCPU(O3CPU *cpu_ptr); -- cgit v1.2.3