From b3f930c884ef23e4d784553fdccc91a772334fd7 Mon Sep 17 00:00:00 2001
From: Andreas Hansson <andreas.hansson@arm.com>
Date: Tue, 17 Jan 2012 12:55:08 -0600
Subject: CPU: Moving towards a more general port across CPU models

This patch performs minimal changes to move the instruction and data
ports from specialised subclasses to the base CPU (to the largest
degree possible). Ultimately it servers to make the CPU(s) have a
well-defined interface to the memory sub-system.
---
 src/cpu/o3/iew.hh | 3 ---
 1 file changed, 3 deletions(-)

(limited to 'src/cpu/o3/iew.hh')

diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
index 113d0756e..c58361cd6 100644
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -139,9 +139,6 @@ class DefaultIEW
     /** Initializes stage; sends back the number of free IQ and LSQ entries. */
     void initStage();
 
-    /** Returns the dcache port. */
-    Port *getDcachePort() { return ldstQueue.getDcachePort(); }
-
     /** Sets main time buffer used for backwards communication. */
     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 
-- 
cgit v1.2.3