From 1716749c8cec6f9c9f10a0aeaff981be759bb4e5 Mon Sep 17 00:00:00 2001
From: Mitch Hayenga <mitch.hayenga@arm.com>
Date: Wed, 3 Sep 2014 07:42:34 -0400
Subject: cpu: Fix o3 front-end pipeline interlock behavior

The o3 pipeline interlock/stall logic is incorrect.  o3 unnecessicarily stalled
fetch and decode due to later stages in the pipeline.  In general, a stage
should usually only consider if it is stalled by the adjacent, downstream stage.
Forcing stalls due to later stages creates and results in bubbles in the
pipeline.  Additionally, o3 stalled the entire frontend (fetch, decode, rename)
on a branch mispredict while the ROB is being serially walked to update the
RAT (robSquashing). Only should have stalled at rename.
---
 src/cpu/o3/iew_impl.hh | 23 ++---------------------
 1 file changed, 2 insertions(+), 21 deletions(-)

(limited to 'src/cpu/o3/iew_impl.hh')

diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index cf2d5be5e..0a4e147c4 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -104,13 +104,12 @@ DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
 
     for (ThreadID tid = 0; tid < numThreads; tid++) {
         dispatchStatus[tid] = Running;
-        stalls[tid].commit = false;
         fetchRedirect[tid] = false;
     }
 
     updateLSQNextCycle = false;
 
-    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
+    skidBufferMax = (renameToIEWDelay + 1) * params->renameWidth;
 }
 
 template <class Impl>
@@ -434,7 +433,6 @@ DefaultIEW<Impl>::takeOverFrom()
 
     for (ThreadID tid = 0; tid < numThreads; tid++) {
         dispatchStatus[tid] = Running;
-        stalls[tid].commit = false;
         fetchRedirect[tid] = false;
     }
 
@@ -760,27 +758,13 @@ DefaultIEW<Impl>::resetEntries()
     ldstQueue.resetEntries();
 }
 
-template <class Impl>
-void
-DefaultIEW<Impl>::readStallSignals(ThreadID tid)
-{
-    if (fromCommit->commitBlock[tid]) {
-        stalls[tid].commit = true;
-    }
-
-    if (fromCommit->commitUnblock[tid]) {
-        assert(stalls[tid].commit);
-        stalls[tid].commit = false;
-    }
-}
-
 template <class Impl>
 bool
 DefaultIEW<Impl>::checkStall(ThreadID tid)
 {
     bool ret_val(false);
 
-    if (stalls[tid].commit) {
+    if (fromCommit->commitInfo[tid].robSquashing) {
         DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
         ret_val = true;
     } else if (instQueue.isFull(tid)) {
@@ -802,8 +786,6 @@ DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
     // If status was Squashing
     //     check if squashing is not high.  Switch to running this cycle.
 
-    readStallSignals(tid);
-
     if (fromCommit->commitInfo[tid].squash) {
         squash(tid);
 
@@ -824,7 +806,6 @@ DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
         dispatchStatus[tid] = Squashing;
         emptyRenameInsts(tid);
         wroteToTimeBuffer = true;
-        return;
     }
 
     if (checkStall(tid)) {
-- 
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