From 4f13f676aa71efaaae2fcd2587cf032a1d70f774 Mon Sep 17 00:00:00 2001
From: Mitch Hayenga <mitch.hayenga@arm.com>
Date: Wed, 3 Sep 2014 07:42:39 -0400
Subject: cpu: Fix cache blocked load behavior in o3 cpu

This patch fixes the load blocked/replay mechanism in the o3 cpu.  Rather than
flushing the entire pipeline, this patch replays loads once the cache becomes
unblocked.

Additionally, deferred memory instructions (loads which had conflicting stores),
when replayed would not respect the number of functional units (only respected
issue width).  This patch also corrects that.

Improvements over 20% have been observed on a microbenchmark designed to
exercise this behavior.
---
 src/cpu/o3/iew_impl.hh | 57 +++++++++++++-------------------------------------
 1 file changed, 14 insertions(+), 43 deletions(-)

(limited to 'src/cpu/o3/iew_impl.hh')

diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 0a4e147c4..448be3a74 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -528,29 +528,6 @@ DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
     }
 }
 
-template<class Impl>
-void
-DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
-{
-    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
-            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
-    if (!toCommit->squash[tid] ||
-            inst->seqNum < toCommit->squashedSeqNum[tid]) {
-        toCommit->squash[tid] = true;
-
-        toCommit->squashedSeqNum[tid] = inst->seqNum;
-        toCommit->pc[tid] = inst->pcState();
-        toCommit->mispredictInst[tid] = NULL;
-
-        // Must include the broadcasted SN in the squash.
-        toCommit->includeSquashInst[tid] = true;
-
-        ldstQueue.setLoadBlockedHandled(tid);
-
-        wroteToTimeBuffer = true;
-    }
-}
-
 template<class Impl>
 void
 DefaultIEW<Impl>::block(ThreadID tid)
@@ -608,6 +585,20 @@ DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
     instQueue.replayMemInst(inst);
 }
 
+template<class Impl>
+void
+DefaultIEW<Impl>::blockMemInst(DynInstPtr& inst)
+{
+    instQueue.blockMemInst(inst);
+}
+
+template<class Impl>
+void
+DefaultIEW<Impl>::cacheUnblocked()
+{
+    instQueue.cacheUnblocked();
+}
+
 template<class Impl>
 void
 DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
@@ -1376,15 +1367,6 @@ DefaultIEW<Impl>::executeInsts()
                 squashDueToMemOrder(violator, tid);
 
                 ++memOrderViolationEvents;
-            } else if (ldstQueue.loadBlocked(tid) &&
-                       !ldstQueue.isLoadBlockedHandled(tid)) {
-                fetchRedirect[tid] = true;
-
-                DPRINTF(IEW, "Load operation couldn't execute because the "
-                        "memory system is blocked.  PC: %s [sn:%lli]\n",
-                        inst->pcState(), inst->seqNum);
-
-                squashDueToMemBlocked(inst, tid);
             }
         } else {
             // Reset any state associated with redirects that will not
@@ -1403,17 +1385,6 @@ DefaultIEW<Impl>::executeInsts()
 
                 ++memOrderViolationEvents;
             }
-            if (ldstQueue.loadBlocked(tid) &&
-                !ldstQueue.isLoadBlockedHandled(tid)) {
-                DPRINTF(IEW, "Load operation couldn't execute because the "
-                        "memory system is blocked.  PC: %s [sn:%lli]\n",
-                        inst->pcState(), inst->seqNum);
-                DPRINTF(IEW, "Blocked load will not be handled because "
-                        "already squashing\n");
-
-                ldstQueue.setLoadBlockedHandled(tid);
-            }
-
         }
     }
 
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