From 976f27487b57e968a326752fcf74747427733df6 Mon Sep 17 00:00:00 2001
From: Mitch Hayenga <mitch.hayenga@arm.com>
Date: Wed, 3 Sep 2014 07:42:33 -0400
Subject: cpu: Change writeback modeling for outstanding instructions

As highlighed on the mailing list gem5's writeback modeling can impact
performance.  This patch removes the limitation on maximum outstanding issued
instructions, however the number that can writeback in a single cycle is still
respected in instToCommit().
---
 src/cpu/o3/iew_impl.hh | 10 ----------
 1 file changed, 10 deletions(-)

(limited to 'src/cpu/o3/iew_impl.hh')

diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh
index 9c6a44bf2..cf2d5be5e 100644
--- a/src/cpu/o3/iew_impl.hh
+++ b/src/cpu/o3/iew_impl.hh
@@ -76,7 +76,6 @@ DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
       issueToExecuteDelay(params->issueToExecuteDelay),
       dispatchWidth(params->dispatchWidth),
       issueWidth(params->issueWidth),
-      wbOutstanding(0),
       wbWidth(params->wbWidth),
       numThreads(params->numThreads)
 {
@@ -109,12 +108,8 @@ DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
         fetchRedirect[tid] = false;
     }
 
-    wbMax = wbWidth * params->wbDepth;
-
     updateLSQNextCycle = false;
 
-    ableToIssue = true;
-
     skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
 }
 
@@ -635,8 +630,6 @@ DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
             ++wbCycle;
             wbNumInst = 0;
         }
-
-        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
     }
 
     DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
@@ -1263,7 +1256,6 @@ DefaultIEW<Impl>::executeInsts()
 
             ++iewExecSquashedInsts;
 
-            decrWb(inst->seqNum);
             continue;
         }
 
@@ -1502,8 +1494,6 @@ DefaultIEW<Impl>::writebackInsts()
             }
             writebackCount[tid]++;
         }
-
-        decrWb(inst->seqNum);
     }
 }
 
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