From 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 Mon Sep 17 00:00:00 2001 From: Yasuko Eckert Date: Tue, 15 Oct 2013 14:22:44 -0400 Subject: cpu: add a condition-code register class Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though. --- src/cpu/o3/inst_queue.hh | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'src/cpu/o3/inst_queue.hh') diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh index 15190970d..212829ec1 100644 --- a/src/cpu/o3/inst_queue.hh +++ b/src/cpu/o3/inst_queue.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 2011-2012 ARM Limited + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * The license below extends only to copyright in the software and shall @@ -414,12 +415,6 @@ class InstructionQueue /** The number of physical registers in the CPU. */ unsigned numPhysRegs; - /** The number of physical integer registers in the CPU. */ - unsigned numPhysIntRegs; - - /** The number of floating point registers in the CPU. */ - unsigned numPhysFloatRegs; - /** Delay between commit stage and the IQ. * @todo: Make there be a distinction between the delays within IEW. */ -- cgit v1.2.3