From 5bfa521c46e489c06ac3ae44b97421f5ccb30bb7 Mon Sep 17 00:00:00 2001
From: Mitch Hayenga <mitch.hayenga@arm.com>
Date: Wed, 29 Oct 2014 23:18:27 -0500
Subject: cpu: Add writeback modeling for drain functionality

It is possible for the O3 CPU to consider itself drained and
later have a squashed instruction perform a writeback.  This
patch re-adds tracking of in-flight instructions to prevent
falsely signaling a drained event.
---
 src/cpu/o3/inst_queue.hh | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'src/cpu/o3/inst_queue.hh')

diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh
index c6c55d08a..23d8d416c 100644
--- a/src/cpu/o3/inst_queue.hh
+++ b/src/cpu/o3/inst_queue.hh
@@ -437,6 +437,9 @@ class InstructionQueue
     /** The number of physical registers in the CPU. */
     unsigned numPhysRegs;
 
+    /** Number of instructions currently in flight to FUs */
+    int wbOutstanding;
+
     /** Delay between commit stage and the IQ.
      *  @todo: Make there be a distinction between the delays within IEW.
      */
-- 
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