From 976f27487b57e968a326752fcf74747427733df6 Mon Sep 17 00:00:00 2001 From: Mitch Hayenga Date: Wed, 3 Sep 2014 07:42:33 -0400 Subject: cpu: Change writeback modeling for outstanding instructions As highlighed on the mailing list gem5's writeback modeling can impact performance. This patch removes the limitation on maximum outstanding issued instructions, however the number that can writeback in a single cycle is still respected in instToCommit(). --- src/cpu/o3/inst_queue_impl.hh | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/cpu/o3/inst_queue_impl.hh') diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh index ab3861add..22f384cf5 100644 --- a/src/cpu/o3/inst_queue_impl.hh +++ b/src/cpu/o3/inst_queue_impl.hh @@ -756,7 +756,6 @@ InstructionQueue::scheduleReadyInsts() int total_issued = 0; while (total_issued < (totalWidth - total_deferred_mem_issued) && - iewStage->canIssue() && order_it != order_end_it) { OpClass op_class = (*order_it).queueType; @@ -861,7 +860,6 @@ InstructionQueue::scheduleReadyInsts() listOrder.erase(order_it++); statIssuedInstType[tid][op_class]++; - iewStage->incrWb(issuing_inst->seqNum); } else { statFuBusy[op_class]++; fuBusy[tid]++; -- cgit v1.2.3