From b4c10bd6800b5ab5adee3035f1908d7a49a14ca9 Mon Sep 17 00:00:00 2001
From: Joel Hestness <hestness@cs.utexas.edu>
Date: Sun, 6 Feb 2011 22:14:17 -0800
Subject: mcpat: Adds McPAT performance counters

Updated patches from Rick Strong's set that modify performance counters for
McPAT
---
 src/cpu/o3/inst_queue_impl.hh | 61 ++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 60 insertions(+), 1 deletion(-)

(limited to 'src/cpu/o3/inst_queue_impl.hh')

diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index ce408dfd0..91cb2f0c8 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -320,6 +320,47 @@ InstructionQueue<Impl>::regStats()
         // Tell mem dependence unit to reg stats as well.
         memDepUnit[tid].regStats();
     }
+
+    intInstQueueReads
+        .name(name() + ".int_inst_queue_reads")
+        .desc("Number of integer instruction queue reads")
+        .flags(total);
+
+    intInstQueueWrites
+        .name(name() + ".int_inst_queue_writes")
+        .desc("Number of integer instruction queue writes")
+        .flags(total);
+
+    intInstQueueWakeupAccesses
+        .name(name() + ".int_inst_queue_wakeup_accesses")
+        .desc("Number of integer instruction queue wakeup accesses")
+        .flags(total);
+
+    fpInstQueueReads
+        .name(name() + ".fp_inst_queue_reads")
+        .desc("Number of floating instruction queue reads")
+        .flags(total);
+
+    fpInstQueueWrites
+        .name(name() + ".fp_inst_queue_writes")
+        .desc("Number of floating instruction queue writes")
+        .flags(total);
+
+    fpInstQueueWakeupQccesses
+        .name(name() + ".fp_inst_queue_wakeup_accesses")
+        .desc("Number of floating instruction queue wakeup accesses")
+        .flags(total);
+
+    intAluAccesses
+        .name(name() + ".int_alu_accesses")
+        .desc("Number of integer alu accesses")
+        .flags(total);
+
+    fpAluAccesses
+        .name(name() + ".fp_alu_accesses")
+        .desc("Number of floating point alu accesses")
+        .flags(total);
+
 }
 
 template <class Impl>
@@ -501,6 +542,7 @@ template <class Impl>
 void
 InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
 {
+    new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
     // Make sure the instruction is valid
     assert(new_inst);
 
@@ -542,6 +584,7 @@ InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
 {
     // @todo: Clean up this code; can do it by setting inst as unable
     // to issue, then calling normal insert on the inst.
+    new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
 
     assert(new_inst);
 
@@ -592,6 +635,11 @@ InstructionQueue<Impl>::getInstToExecute()
     assert(!instsToExecute.empty());
     DynInstPtr inst = instsToExecute.front();
     instsToExecute.pop_front();
+    if (inst->isFloating()){
+        fpInstQueueReads++;
+    } else {
+        intInstQueueReads++;
+    }
     return inst;
 }
 
@@ -706,6 +754,8 @@ InstructionQueue<Impl>::scheduleReadyInsts()
 
         DynInstPtr issuing_inst = readyInsts[op_class].top();
 
+        issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
+
         assert(issuing_inst->seqNum == (*order_it).oldestInst);
 
         if (issuing_inst->isSquashed()) {
@@ -731,7 +781,7 @@ InstructionQueue<Impl>::scheduleReadyInsts()
 
         if (op_class != No_OpClass) {
             idx = fuPool->getUnit(op_class);
-
+            issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
             if (idx > -1) {
                 op_latency = fuPool->getOpLatency(op_class);
             }
@@ -867,6 +917,13 @@ InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
 {
     int dependents = 0;
 
+    // The instruction queue here takes care of both floating and int ops
+    if (completed_inst->isFloating()) {
+        fpInstQueueWakeupQccesses++;
+    } else {
+        intInstQueueWakeupAccesses++;
+    }
+
     DPRINTF(IQ, "Waking dependents of completed instruction.\n");
 
     assert(!completed_inst->isSquashed());
@@ -997,6 +1054,7 @@ void
 InstructionQueue<Impl>::violation(DynInstPtr &store,
                                   DynInstPtr &faulting_load)
 {
+    intInstQueueWrites++;
     memDepUnit[store->threadNumber].violation(store, faulting_load);
 }
 
@@ -1037,6 +1095,7 @@ InstructionQueue<Impl>::doSquash(ThreadID tid)
            (*squash_it)->seqNum > squashedSeqNum[tid]) {
 
         DynInstPtr squashed_inst = (*squash_it);
+        squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
 
         // Only handle the instruction if it actually is in the IQ and
         // hasn't already been squashed in the IQ.
-- 
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