From 0ca254aa8381ba2fae61a4a056301e35da9ffab3 Mon Sep 17 00:00:00 2001
From: Iru Cai <mytbk920423@gmail.com>
Date: Thu, 28 Feb 2019 17:07:16 +0800
Subject: invisispec-1.0 source

---
 src/cpu/o3/lsq.hh | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

(limited to 'src/cpu/o3/lsq.hh')

diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 7c78156d5..518153990 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -136,6 +136,23 @@ class LSQ {
     /** Same as above, but only for one thread. */
     void writebackStores(ThreadID tid);
 
+
+    /** [mengjia]
+     * Attempts to validate loads until all cache ports are used or the
+     * interface becomes blocked.
+     */
+    int exposeLoads();
+    /** Same as above, but only for one thread. */
+    int exposeLoads(ThreadID tid);
+
+    /** [mengjia]
+     * attempt to update FenceDelay state for load insts
+     */
+    void updateVisibleState();
+    /** Same as above, but only for one thread. */
+    void updateVisibleState(ThreadID tid);
+
+
     /**
      * Squash instructions from a thread until the specified sequence number.
      */
@@ -257,6 +274,10 @@ class LSQ {
     int numStoresToWB(ThreadID tid)
     { return thread[tid].numStoresToWB(); }
 
+    /** Returns the number of stores a specific thread has to write back. */
+    int numLoadsToVLD(ThreadID tid)
+    { return thread[tid].numLoadsToVLD(); }
+
     /** Returns if the LSQ will write back to memory this cycle. */
     bool willWB();
     /** Returns if the LSQ of a specific thread will write back to memory this
-- 
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