From 9c582c7e144aef0bfc9d14bb4690d56d1688496a Mon Sep 17 00:00:00 2001
From: Ron Dreslinski <rdreslin@umich.edu>
Date: Tue, 17 Oct 2006 18:50:19 -0400
Subject: Fixes for uni-coherence in timing mode for FS. Still a bug in atomic
 uni-coherence in FS.

src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
    Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
    Only deallocate once

--HG--
extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
---
 src/cpu/o3/lsq_impl.hh | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'src/cpu/o3/lsq_impl.hh')

diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 7b7d1eb8e..337ee0372 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -63,7 +63,14 @@ template <class Impl>
 bool
 LSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
 {
-    lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
+    if (pkt->isResponse()) {
+        lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
+    }
+    else {
+    //else it is a coherence request, maybe you need to do something
+        warn("Recieved a coherence request (Invalidate??), 03CPU doesn't"
+             "update LSQ for these\n");
+    }
     return true;
 }
 
-- 
cgit v1.2.3