From ad4483490785236f49b009f0d7ef3328abaf8cc5 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Fri, 9 Mar 2007 10:06:09 -0500
Subject: Two fixes: 1. Make sure connectMemPorts() only gets called when the
 CPU's peer gets changed.  This is done by making setPeer() virtual, and
 overriding it in the CPU's ports.  When it gets called on a CPU's port
 (dcache specifically), it calls the normal setPeer() function, and also
 connectMemPorts(). 2. Consolidate redundant code that handles switching in a
 CPU.

src/cpu/base.cc:
    Move common code of switching over peers to base CPU.
src/cpu/base.hh:
    Move common code of switching over peers to BaseCPU.
src/cpu/o3/cpu.cc:
    Add in function that updates thread context's ports.
    Also use updated function to takeOverFrom() in BaseCPU.  This gets rid of some repeated code.
src/cpu/o3/cpu.hh:
    Include function to update thread context's memory ports.
src/cpu/o3/lsq.hh:
    Add function to dcache port that will update the memory ports upon getting a new peer.
    Also include a function that will tell the CPU to update those memory ports.
src/cpu/o3/lsq_impl.hh:
    Add function that will update the memory ports upon getting a new peer.
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Add function that will update thread context's memory ports upon getting a new peer.
    Also use the new BaseCPU's take over from function.
src/cpu/simple/atomic.hh:
    Add in function (and dcache port) that will allow the dcache to update memory ports when it gets assigned a new peer.
src/cpu/simple/timing.hh:
    Add function that will update thread context's memory ports upon getting a new peer.
src/mem/port.hh:
    Make setPeer virtual so that other classes can override it.

--HG--
extra : convert_revision : 2050f1241dd2e83875d281cfc5ad5c6c8705fdaf
---
 src/cpu/o3/lsq_impl.hh | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'src/cpu/o3/lsq_impl.hh')

diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index fb738f7c9..d4994fcb7 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -34,6 +34,19 @@
 
 #include "cpu/o3/lsq.hh"
 
+template<class Impl>
+void
+LSQ<Impl>::DcachePort::setPeer(Port *port)
+{
+    Port::setPeer(port);
+
+#if FULL_SYSTEM
+    // Update the ThreadContext's memory ports (Functional/Virtual
+    // Ports)
+    lsq->updateMemPorts();
+#endif
+}
+
 template <class Impl>
 Tick
 LSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
-- 
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