From 090496bf2d4c0f55f7f5869a374b4ec3826bccbc Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Mon, 5 Jun 2006 18:14:39 -0400
Subject: Fixes to get new CPU model working for simple test case.  The CPU
 does not yet support retrying accesses.

src/cpu/base_dyn_inst.cc:
    Delete the allocated data in destructor.
src/cpu/base_dyn_inst.hh:
    Only copy the addresses if the translation succeeded.
src/cpu/o3/alpha_cpu.hh:
    Return actual translating port.
    Don't panic on setNextNPC() as it's always called, regardless of the architecture, when the process initializes.
src/cpu/o3/alpha_cpu_impl.hh:
    Pass in memobject to the thread state in SE mode.
src/cpu/o3/commit_impl.hh:
    Initialize all variables.
src/cpu/o3/decode_impl.hh:
    Handle early resolution of branches properly.
src/cpu/o3/fetch.hh:
    Switch structure back to requests.
src/cpu/o3/fetch_impl.hh:
    Initialize all variables, create/delete requests properly.
src/cpu/o3/lsq_unit.hh:
    Include sender state along with the packet.  Also include a more generic writeback event that's only used for stores forwarding data to loads.
src/cpu/o3/lsq_unit_impl.hh:
    Redo writeback code to support the response path of the memory system.
src/cpu/o3/mem_dep_unit.cc:
src/cpu/o3/mem_dep_unit_impl.hh:
    Wrap variables in #ifdefs.
src/cpu/o3/store_set.cc:
    Include to get panic() function.
src/cpu/o3/thread_state.hh:
    Create with MemObject as well.
src/cpu/thread_state.hh:
    Have a translating port in the thread state object.
src/python/m5/objects/AlphaFullCPU.py:
    Mem parameter no longer needed.

--HG--
extra : convert_revision : a99381fb25cb183322882ce20935a6f3d1f2b64d
---
 src/cpu/o3/lsq_unit.hh | 61 ++++++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 52 insertions(+), 9 deletions(-)

(limited to 'src/cpu/o3/lsq_unit.hh')

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 393d8947d..414309679 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -130,8 +130,6 @@ class LSQUnit {
 
     void completeDataAccess(PacketPtr pkt);
 
-    void completeStoreDataAccess(DynInstPtr &inst);
-
     // @todo: Include stats in the LSQ unit.
     //void regStats();
 
@@ -206,10 +204,12 @@ class LSQUnit {
 
     /** Returns if the LSQ unit will writeback on this cycle. */
     bool willWB() { return storeQueue[storeWBIdx].canWB &&
-                        !storeQueue[storeWBIdx].completed/* &&
-                                                            !dcacheInterface->isBlocked()*/; }
+                        !storeQueue[storeWBIdx].completed &&
+                        !isStoreBlocked; }
 
   private:
+    void writeback(DynInstPtr &inst, PacketPtr pkt);
+
     /** Completes the store at the specified index. */
     void completeStore(int store_idx);
 
@@ -265,9 +265,43 @@ class LSQUnit {
     /** Pointer to the D-cache. */
     DcachePort *dcachePort;
 
+    class LSQSenderState : public Packet::SenderState
+    {
+      public:
+        LSQSenderState()
+            : noWB(false)
+        { }
+
+//      protected:
+        DynInstPtr inst;
+        bool isLoad;
+        int idx;
+        bool noWB;
+    };
+
     /** Pointer to the page table. */
 //    PageTable *pTable;
 
+    class WritebackEvent : public Event {
+      public:
+        /** Constructs a writeback event. */
+        WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr);
+
+        /** Processes the writeback event. */
+        void process();
+
+        /** Returns the description of this event. */
+        const char *description();
+
+      private:
+        DynInstPtr inst;
+
+        PacketPtr pkt;
+
+        /** The pointer to the LSQ unit that issued the store. */
+        LSQUnit<Impl> *lsqPtr;
+    };
+
   public:
     struct SQEntry {
         /** Constructs an empty store queue entry. */
@@ -362,6 +396,8 @@ class LSQUnit {
     /** The index of the above store. */
     int stallingLoadIdx;
 
+    bool isStoreBlocked;
+
     /** Whether or not a load is blocked due to the memory system. */
     bool isLoadBlocked;
 
@@ -521,16 +557,17 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
             DPRINTF(LSQUnit, "Forwarding from store idx %i to load to "
                     "addr %#x, data %#x\n",
                     store_idx, req->getVaddr(), *(load_inst->memData));
-/*
-            typename LdWritebackEvent *wb =
-                new typename LdWritebackEvent(load_inst,
-                                              iewStage);
+
+            PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
+            data_pkt->dataStatic(load_inst->memData);
+
+            WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
 
             // We'll say this has a 1 cycle load-store forwarding latency
             // for now.
             // @todo: Need to make this a parameter.
             wb->schedule(curTick);
-*/
+
             // Should keep track of stat for forwarded data
             return NoFault;
         } else if ((store_has_lower_limit && lower_load_has_store_part) ||
@@ -585,6 +622,12 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
     PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
     data_pkt->dataStatic(load_inst->memData);
 
+    LSQSenderState *state = new LSQSenderState;
+    state->isLoad = true;
+    state->idx = load_idx;
+    state->inst = load_inst;
+    data_pkt->senderState = state;
+
     // if we have a cache, do cache access too
     if (!dcachePort->sendTiming(data_pkt)) {
         // There's an older load that's already going to squash.
-- 
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