From 0b3897fc90901953e9d016466c37ab507f85023c Mon Sep 17 00:00:00 2001 From: Anthony Gutierrez Date: Wed, 15 Aug 2012 10:38:08 -0400 Subject: O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs This patch fixes some problems with the drain/switchout functionality for the O3 cpu and for the ARM ISA and adds some useful debug print statements. This is an incremental fix as there are still a few bugs/mem leaks with the switchout code. Particularly when switching from an O3CPU to a TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA I haven't encountered any more assertion failures; now the kernel will typically panic inside of simulation. --- src/cpu/o3/lsq_unit.hh | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/cpu/o3/lsq_unit.hh') diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 7093b5fee..b886a2259 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -335,6 +335,11 @@ class LSQUnit { std::memset(data, 0, sizeof(data)); } + ~SQEntry() + { + inst = NULL; + } + /** Constructs a store queue entry for a given instruction. */ SQEntry(DynInstPtr &_inst) : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0), -- cgit v1.2.3