From 206c2e9a0ee04e00100dde25da9b15cbfbaac0d6 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 31 Jul 2011 19:21:17 -0700
Subject: O3: Implement memory mapped IPRs for O3.

---
 src/cpu/o3/lsq_unit.hh | 38 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

(limited to 'src/cpu/o3/lsq_unit.hh')

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index d83dc868f..2076d67d1 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -39,6 +39,7 @@
 
 #include "arch/faults.hh"
 #include "arch/locked_mem.hh"
+#include "arch/mmapped_ipr.hh"
 #include "base/fast_alloc.hh"
 #include "base/hashmap.hh"
 #include "config/full_system.hh"
@@ -578,6 +579,43 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
         load_inst->recordResult = true;
     }
 
+    if (req->isMmappedIpr()) {
+        assert(!load_inst->memData);
+        load_inst->memData = new uint8_t[64];
+
+        ThreadContext *thread = cpu->tcBase(lsqID);
+        Tick delay;
+        PacketPtr data_pkt =
+            new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
+
+        if (!TheISA::HasUnalignedMemAcc || !sreqLow) {
+            data_pkt->dataStatic(load_inst->memData);
+            delay = TheISA::handleIprRead(thread, data_pkt);
+        } else {
+            assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr());
+            PacketPtr fst_data_pkt =
+                new Packet(sreqLow, MemCmd::ReadReq, Packet::Broadcast);
+            PacketPtr snd_data_pkt =
+                new Packet(sreqHigh, MemCmd::ReadReq, Packet::Broadcast);
+
+            fst_data_pkt->dataStatic(load_inst->memData);
+            snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize());
+
+            delay = TheISA::handleIprRead(thread, fst_data_pkt);
+            unsigned delay2 = TheISA::handleIprRead(thread, snd_data_pkt);
+            if (delay2 > delay)
+                delay = delay2;
+
+            delete sreqLow;
+            delete sreqHigh;
+            delete fst_data_pkt;
+            delete snd_data_pkt;
+        }
+        WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
+        cpu->schedule(wb, curTick() + delay);
+        return NoFault;
+    }
+
     while (store_idx != -1) {
         // End once we've reached the top of the LSQ
         if (store_idx == storeWBIdx) {
-- 
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