From 43c938d23e2b28c7190bd10c470c452676f5cb9d Mon Sep 17 00:00:00 2001 From: Min Kyu Jeong Date: Mon, 23 Aug 2010 11:18:40 -0500 Subject: O3: Handle loads when the destination is the PC. For loads that PC is the destination, check if the load was mispredicted again when the value being loaded returns from memory --- src/cpu/o3/lsq_unit.hh | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/cpu/o3/lsq_unit.hh') diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 10b1ed11a..a9047558d 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -530,6 +530,8 @@ LSQUnit::read(Request *req, Request *sreqLow, Request *sreqHigh, (load_idx != loadHead || !load_inst->isAtCommit())) { iewStage->rescheduleMemInst(load_inst); ++lsqRescheduledLoads; + DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %#x\n", + load_inst->seqNum, load_inst->readPC()); // Must delete request now that it wasn't handed off to // memory. This is quite ugly. @todo: Figure out the proper -- cgit v1.2.3