From 2f043aafbcb039c11870c707f5d64e00f9693151 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Tue, 13 Jun 2006 22:35:05 -0400
Subject: Minor updates for stats.

src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch.hh:
    Update stats comments.
src/cpu/o3/fetch_impl.hh:
    Differentiate stats.
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
    Update for stats.
src/cpu/o3/lsq.hh:
    LSQ now has stats.
src/cpu/o3/lsq_impl.hh:
    Register stats of all LSQ units.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Add in stats.

--HG--
extra : convert_revision : 7672ecf3c02515b268c28d5a986af1432197654a
---
 src/cpu/o3/lsq_unit.hh | 50 ++++++++++++++++++++++++++++++++------------------
 1 file changed, 32 insertions(+), 18 deletions(-)

(limited to 'src/cpu/o3/lsq_unit.hh')

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index ce0cdd36f..3de581519 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -77,6 +77,9 @@ class LSQUnit {
     /** Returns the name of the LSQ unit. */
     std::string name() const;
 
+    /** Registers statistics. */
+    void regStats();
+
     /** Sets the CPU pointer. */
     void setCPU(FullCPU *cpu_ptr);
 
@@ -127,9 +130,6 @@ class LSQUnit {
 
     void completeDataAccess(PacketPtr pkt);
 
-    // @todo: Include stats in the LSQ unit.
-    //void regStats();
-
     /** Clears all the entries in the LQ. */
     void clearLQ();
 
@@ -443,25 +443,35 @@ class LSQUnit {
     // Will also need how many read/write ports the Dcache has.  Or keep track
     // of that in stage that is one level up, and only call executeLoad/Store
     // the appropriate number of times.
-/*
-    // total number of loads forwaded from LSQ stores
-    Stats::Vector<> lsq_forw_loads;
 
-    // total number of loads ignored due to invalid addresses
-    Stats::Vector<> inv_addr_loads;
+    /** Total number of loads forwaded from LSQ stores. */
+    Stats::Scalar<> lsqForwLoads;
+
+    /** Total number of loads ignored due to invalid addresses. */
+    Stats::Scalar<> invAddrLoads;
+
+    /** Total number of squashed loads. */
+    Stats::Scalar<> lsqSquashedLoads;
+
+    /** Total number of responses from the memory system that are
+     * ignored due to the instruction already being squashed. */
+    Stats::Scalar<> lsqIgnoredResponses;
+
+    /** Total number of squashed stores. */
+    Stats::Scalar<> lsqSquashedStores;
+
+    /** Total number of software prefetches ignored due to invalid addresses. */
+    Stats::Scalar<> invAddrSwpfs;
 
-    // total number of software prefetches ignored due to invalid addresses
-    Stats::Vector<> inv_addr_swpfs;
+    /** Ready loads blocked due to partial store-forwarding. */
+    Stats::Scalar<> lsqBlockedLoads;
 
-    // total non-speculative bogus addresses seen (debug var)
-    Counter sim_invalid_addrs;
-    Stats::Vector<> fu_busy;  //cumulative fu busy
+    /** Number of loads that were rescheduled. */
+    Stats::Scalar<> lsqRescheduledLoads;
 
-    // ready loads blocked due to memory disambiguation
-    Stats::Vector<> lsq_blocked_loads;
+    /** Number of times the LSQ is blocked due to the cache. */
+    Stats::Scalar<> lsqCacheBlocked;
 
-    Stats::Scalar<> lsqInversion;
-*/
   public:
     /** Executes the load at the given index. */
     template <class T>
@@ -519,6 +529,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
     if (req->getFlags() & UNCACHEABLE &&
         (load_idx != loadHead || !load_inst->reachedCommit)) {
         iewStage->rescheduleMemInst(load_inst);
+        ++lsqRescheduledLoads;
         return TheISA::genMachineCheckFault();
     }
 
@@ -598,7 +609,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
             // @todo: Need to make this a parameter.
             wb->schedule(curTick);
 
-            // Should keep track of stat for forwarded data
+            ++lsqForwLoads;
             return NoFault;
         } else if ((store_has_lower_limit && lower_load_has_store_part) ||
                    (store_has_upper_limit && upper_load_has_store_part) ||
@@ -626,6 +637,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
             // Tell IQ/mem dep unit that this instruction will need to be
             // rescheduled eventually
             iewStage->rescheduleMemInst(load_inst);
+            ++lsqRescheduledLoads;
 
             // Do not generate a writeback event as this instruction is not
             // complete.
@@ -633,6 +645,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
                     "Store idx %i to load addr %#x\n",
                     store_idx, req->getVaddr());
 
+            ++lsqBlockedLoads;
             return NoFault;
         }
     }
@@ -660,6 +673,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
 
     // if we have a cache, do cache access too
     if (!dcachePort->sendTiming(data_pkt)) {
+        ++lsqCacheBlocked;
         // There's an older load that's already going to squash.
         if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum)
             return NoFault;
-- 
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