From e50a880297f13817200f4e74272ad1cf3194d401 Mon Sep 17 00:00:00 2001 From: "Timothy M. Jones" Date: Thu, 22 Jul 2010 18:52:02 +0100 Subject: O3CPU: Fix a bug where stores in the cpu where never marked as split. --- src/cpu/o3/lsq_unit.hh | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/cpu/o3/lsq_unit.hh') diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index cf51f8eab..7b8b1e2e3 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -822,6 +822,12 @@ LSQUnit::write(Request *req, Request *sreqLow, Request *sreqHigh, storeQueue[store_idx].sreqLow = sreqLow; storeQueue[store_idx].sreqHigh = sreqHigh; storeQueue[store_idx].size = sizeof(T); + + // Split stores can only occur in ISAs with unaligned memory accesses. If + // a store request has been split, sreqLow and sreqHigh will be non-null. + if (TheISA::HasUnalignedMemAcc && sreqLow) { + storeQueue[store_idx].isSplit = true; + } assert(sizeof(T) <= sizeof(storeQueue[store_idx].data)); T gData = htog(data); -- cgit v1.2.3