From 2f043aafbcb039c11870c707f5d64e00f9693151 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Tue, 13 Jun 2006 22:35:05 -0400
Subject: Minor updates for stats.

src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch.hh:
    Update stats comments.
src/cpu/o3/fetch_impl.hh:
    Differentiate stats.
src/cpu/o3/iew.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue.hh:
src/cpu/o3/inst_queue_impl.hh:
    Update for stats.
src/cpu/o3/lsq.hh:
    LSQ now has stats.
src/cpu/o3/lsq_impl.hh:
    Register stats of all LSQ units.
src/cpu/o3/lsq_unit.hh:
src/cpu/o3/lsq_unit_impl.hh:
    Add in stats.

--HG--
extra : convert_revision : 7672ecf3c02515b268c28d5a986af1432197654a
---
 src/cpu/o3/lsq_unit_impl.hh | 47 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 46 insertions(+), 1 deletion(-)

(limited to 'src/cpu/o3/lsq_unit_impl.hh')

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 4c01f29a2..a5c1eb12a 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -196,6 +196,47 @@ LSQUnit<Impl>::name() const
     }
 }
 
+template<class Impl>
+void
+LSQUnit<Impl>::regStats()
+{
+    lsqForwLoads
+        .name(name() + ".forwLoads")
+        .desc("Number of loads that had data forwarded from stores");
+
+    invAddrLoads
+        .name(name() + ".invAddrLoads")
+        .desc("Number of loads ignored due to an invalid address");
+
+    lsqSquashedLoads
+        .name(name() + ".squashedLoads")
+        .desc("Number of loads squashed");
+
+    lsqIgnoredResponses
+        .name(name() + ".ignoredResponses")
+        .desc("Number of memory responses ignored because the instruction is squashed");
+
+    lsqSquashedStores
+        .name(name() + ".squashedStores")
+        .desc("Number of stores squashed");
+
+    invAddrSwpfs
+        .name(name() + ".invAddrSwpfs")
+        .desc("Number of software prefetches ignored due to an invalid address");
+
+    lsqBlockedLoads
+        .name(name() + ".blockedLoads")
+        .desc("Number of blocked loads due to partial load-store forwarding");
+
+    lsqRescheduledLoads
+        .name(name() + ".rescheduledLoads")
+        .desc("Number of loads that were rescheduled");
+
+    lsqCacheBlocked
+        .name(name() + ".cacheBlocked")
+        .desc("Number of times an access to memory failed due to the cache being blocked");
+}
+
 template<class Impl>
 void
 LSQUnit<Impl>::clearLQ()
@@ -618,7 +659,7 @@ LSQUnit<Impl>::writebackStores()
         if (!dcachePort->sendTiming(data_pkt)) {
             // Need to handle becoming blocked on a store.
             isStoreBlocked = true;
-
+            ++lsqCacheBlocked;
             assert(retryPkt == NULL);
             retryPkt = data_pkt;
         } else {
@@ -677,6 +718,7 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
         loadTail = load_idx;
 
         decrLdIdx(load_idx);
+        ++lsqSquashedLoads;
     }
 
     if (isLoadBlocked) {
@@ -723,6 +765,7 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
         storeTail = store_idx;
 
         decrStIdx(store_idx);
+        ++lsqSquashedStores;
     }
 }
 
@@ -782,6 +825,7 @@ LSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
     // Squashed instructions do not need to complete their access.
     if (inst->isSquashed()) {
         assert(!inst->isStore());
+        ++lsqIgnoredResponses;
         return;
     }
 
@@ -858,6 +902,7 @@ LSQUnit<Impl>::recvRetry()
             isStoreBlocked = false;
         } else {
             // Still blocked!
+            ++lsqCacheBlocked;
         }
     } else if (isLoadBlocked) {
         DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, "
-- 
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