From 810349a8a789b0a99d6268fe725eca2e00cb9558 Mon Sep 17 00:00:00 2001 From: Stephan Diestelhorst Date: Tue, 2 Dec 2014 06:07:58 -0500 Subject: cpu: Move packet deallocation to recvTimingResp in the O3 CPU Move the packet deallocations in the O3 CPU so that the completeDataAccess deals only with the LSQ specific parts and the generic recvTimingResp frees the packet in all other cases. --- src/cpu/o3/lsq_unit_impl.hh | 6 ------ 1 file changed, 6 deletions(-) (limited to 'src/cpu/o3/lsq_unit_impl.hh') diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 887e971b4..0cc412811 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -105,15 +105,11 @@ LSQUnit::completeDataAccess(PacketPtr pkt) DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier " "blocked split load recieved. Ignoring.\n", inst->seqNum); delete state; - delete pkt->req; - delete pkt; return; } // If this is a split access, wait until all packets are received. if (TheISA::HasUnalignedMemAcc && !state->complete()) { - delete pkt->req; - delete pkt; return; } @@ -142,8 +138,6 @@ LSQUnit::completeDataAccess(PacketPtr pkt) cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); delete state; - delete pkt->req; - delete pkt; } template -- cgit v1.2.3