From 98c8cd0b36c31a30229d408ddb9e397e8d1364fe Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Tue, 3 Apr 2007 14:25:24 -0400
Subject: Fix a memory leak.  Hopefully this fixes the longer running
 benchmarks.

--HG--
extra : convert_revision : 89eff82642ff181a9b95c77c4d2bf620ca837113
---
 src/cpu/o3/lsq_unit_impl.hh | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'src/cpu/o3/lsq_unit_impl.hh')

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 0a3021046..493144919 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -57,6 +57,11 @@ LSQUnit<Impl>::WritebackEvent::process()
     if (!lsqPtr->isSwitchedOut()) {
         lsqPtr->writeback(inst, pkt);
     }
+
+    if (pkt->senderState)
+        delete pkt->senderState;
+
+    delete pkt->req;
     delete pkt;
 }
 
@@ -80,10 +85,6 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
 
     if (isSwitchedOut() || inst->isSquashed()) {
         iewStage->decrWb(inst->seqNum);
-        delete state;
-        delete pkt->req;
-        delete pkt;
-        return;
     } else {
         if (!state->noWB) {
             writeback(inst, pkt);
-- 
cgit v1.2.3


From 6ff6621f20eb6513e12c769f601dba0b47b47697 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Wed, 4 Apr 2007 15:38:59 -0400
Subject: Pass ISA-specific O3 CPU as a constructor parameter instead of using
 setCPU functions.

src/cpu/o3/alpha/cpu_impl.hh:
    Pass ISA-specific O3 CPU to FullO3CPU as a constructor parameter instead of using setCPU functions.

--HG--
extra : convert_revision : 74f4b1f5fb6f95a56081f367cce7ff44acb5688a
---
 src/cpu/o3/lsq_unit_impl.hh | 35 +++++++++++++++++++----------------
 1 file changed, 19 insertions(+), 16 deletions(-)

(limited to 'src/cpu/o3/lsq_unit_impl.hh')

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 493144919..2aa0d6b6a 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -110,10 +110,13 @@ LSQUnit<Impl>::LSQUnit()
 
 template<class Impl>
 void
-LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
-                    unsigned maxSQEntries, unsigned id)
+LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
+                    unsigned maxLQEntries, unsigned maxSQEntries, unsigned id)
 {
-//    DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
+    cpu = cpu_ptr;
+    iewStage = iew_ptr;
+
+    DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
 
     switchedOut = false;
 
@@ -141,19 +144,6 @@ LSQUnit<Impl>::init(Params *params, LSQ *lsq_ptr, unsigned maxLQEntries,
     blockedLoadSeqNum = 0;
 }
 
-template<class Impl>
-void
-LSQUnit<Impl>::setCPU(O3CPU *cpu_ptr)
-{
-    cpu = cpu_ptr;
-
-#if USE_CHECKER
-    if (cpu->checker) {
-        cpu->checker->setDcachePort(dcachePort);
-    }
-#endif
-}
-
 template<class Impl>
 std::string
 LSQUnit<Impl>::name() const
@@ -210,6 +200,19 @@ LSQUnit<Impl>::regStats()
         .desc("Number of times an access to memory failed due to the cache being blocked");
 }
 
+template<class Impl>
+void
+LSQUnit<Impl>::setDcachePort(Port *dcache_port)
+{
+    dcachePort = dcache_port;
+
+#if USE_CHECKER
+    if (cpu->checker) {
+        cpu->checker->setDcachePort(dcachePort);
+    }
+#endif
+}
+
 template<class Impl>
 void
 LSQUnit<Impl>::clearLQ()
-- 
cgit v1.2.3