From ca89eba79ebe0adc9cea7656c288e0381754171a Mon Sep 17 00:00:00 2001
From: Matt Horsnell <matt.horsnell@ARM.com>
Date: Fri, 24 Jan 2014 15:29:30 -0600
Subject: mem: track per-request latencies and access depths in the cache
 hierarchy

Add some values and methods to the request object to track the translation
and access latency for a request and which level of the cache hierarchy responded
to the request.
---
 src/cpu/o3/lsq_unit_impl.hh | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/cpu/o3/lsq_unit_impl.hh')

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 77b67ac69..ade076995 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -129,6 +129,8 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
         delete state->mainPkt->req;
         delete state->mainPkt;
     }
+
+    pkt->req->setAccessLatency();
     delete state;
     delete pkt->req;
     delete pkt;
-- 
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