From f54020eb8155371725ab75b0fc5c419287eca084 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Mon, 4 Jun 2018 09:40:19 +0100
Subject: misc: Using smart pointers for memory Requests

This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.

Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
---
 src/cpu/o3/lsq_unit_impl.hh | 22 ++++++----------------
 1 file changed, 6 insertions(+), 16 deletions(-)

(limited to 'src/cpu/o3/lsq_unit_impl.hh')

diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index e8e2c1853..c2750be7d 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -79,7 +79,6 @@ LSQUnit<Impl>::WritebackEvent::process()
     if (pkt->senderState)
         delete pkt->senderState;
 
-    delete pkt->req;
     delete pkt;
 }
 
@@ -133,7 +132,6 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
     }
 
     if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) {
-        delete state->mainPkt->req;
         delete state->mainPkt;
     }
 
@@ -831,9 +829,9 @@ LSQUnit<Impl>::writebackStores()
 
         DynInstPtr inst = storeQueue[storeWBIdx].inst;
 
-        RequestPtr req = storeQueue[storeWBIdx].req;
-        RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow;
-        RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh;
+        RequestPtr &req = storeQueue[storeWBIdx].req;
+        const RequestPtr &sreqLow = storeQueue[storeWBIdx].sreqLow;
+        const RequestPtr &sreqHigh = storeQueue[storeWBIdx].sreqHigh;
 
         storeQueue[storeWBIdx].committed = true;
 
@@ -874,7 +872,6 @@ LSQUnit<Impl>::writebackStores()
             state->outstanding = 2;
 
             // Can delete the main request now.
-            delete req;
             req = sreqLow;
         }
 
@@ -923,11 +920,8 @@ LSQUnit<Impl>::writebackStores()
                 assert(snd_data_pkt->req->isMmappedIpr());
                 TheISA::handleIprWrite(thread, snd_data_pkt);
                 delete snd_data_pkt;
-                delete sreqLow;
-                delete sreqHigh;
             }
             delete state;
-            delete req;
             completeStore(storeWBIdx);
             incrStIdx(storeWBIdx);
         } else if (!sendStore(data_pkt)) {
@@ -1061,16 +1055,12 @@ LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
         // Must delete request now that it wasn't handed off to
         // memory.  This is quite ugly.  @todo: Figure out the proper
         // place to really handle request deletes.
-        delete storeQueue[store_idx].req;
+        storeQueue[store_idx].req.reset();
         if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) {
-            delete storeQueue[store_idx].sreqLow;
-            delete storeQueue[store_idx].sreqHigh;
-
-            storeQueue[store_idx].sreqLow = NULL;
-            storeQueue[store_idx].sreqHigh = NULL;
+            storeQueue[store_idx].sreqLow.reset();
+            storeQueue[store_idx].sreqHigh.reset();
         }
 
-        storeQueue[store_idx].req = NULL;
         --stores;
 
         // Inefficient!
-- 
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