From d1e533a1e243b75b3257e2f96deb385a3b10e09b Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Thu, 26 Jul 2007 22:13:14 -0700
Subject: X86: Fix argument register indexing. Code was assuming that all
 argument registers followed in order from ArgumentReg0. There is now an
 ArgumentReg array which is indexed to find the right index. There is a
 constant, NumArgumentRegs, which can be used to protect against using an
 invalid ArgumentReg.

--HG--
extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
---
 src/cpu/o3/sparc/cpu_impl.hh | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'src/cpu/o3/sparc/cpu_impl.hh')

diff --git a/src/cpu/o3/sparc/cpu_impl.hh b/src/cpu/o3/sparc/cpu_impl.hh
index 2e398577e..068057fc0 100644
--- a/src/cpu/o3/sparc/cpu_impl.hh
+++ b/src/cpu/o3/sparc/cpu_impl.hh
@@ -270,8 +270,9 @@ template <class Impl>
 TheISA::IntReg
 SparcO3CPU<Impl>::getSyscallArg(int i, int tid)
 {
+    assert(i < TheISA::NumArgumentRegs);
     TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
-            SparcISA::ArgumentReg0 + i);
+            SparcISA::ArgumentReg[i]);
     TheISA::IntReg val = this->readArchIntReg(idx, tid);
     if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3))
         val = bits(val, 31, 0);
@@ -282,8 +283,9 @@ template <class Impl>
 void
 SparcO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid)
 {
+    assert(i < TheISA::NumArgumentRegs);
     TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
-            SparcISA::ArgumentReg0 + i);
+            SparcISA::ArgumentReg[i]);
     this->setArchIntReg(idx, val, tid);
 }
 
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