From 5f425b8bd1ac70b61fc57b7ec44c52cd7d8de9fb Mon Sep 17 00:00:00 2001 From: Geoffrey Blake Date: Fri, 19 Aug 2011 15:08:07 -0500 Subject: Fix bugs due to interaction between SEV instructions and O3 pipeline SEV instructions were originally implemented to cause asynchronous squashes via the generateTCSquash() function in the O3 pipeline when updating the SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system that would lead to a pipeline either going inactive indefinitely or not being able to commit squashed instructions. Fixed SEV instructions to behave like interrupts and cause synchronous sqaushes inside the pipeline, eliminating the race conditions. Also fixed up the semantics of the WFE instruction to behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1 or unmasked interrupts are pending. --- src/cpu/o3/thread_context_impl.hh | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/cpu/o3/thread_context_impl.hh') diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index c3b7d2248..4888cf92e 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -351,8 +351,7 @@ O3ThreadContext::setMiscRegNoEffect(int misc_reg, const MiscReg &val) template void -O3ThreadContext::setMiscReg(int misc_reg, - const MiscReg &val) +O3ThreadContext::setMiscReg(int misc_reg, const MiscReg &val) { cpu->setMiscReg(misc_reg, val, thread->threadId()); -- cgit v1.2.3