From 005892719047c3b4b383d9aeeeb481039518f661 Mon Sep 17 00:00:00 2001
From: Giacomo Gabrielli <Giacomo.Gabrielli@arm.com>
Date: Mon, 15 Nov 2010 14:04:04 -0600
Subject: CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.

---
 src/cpu/o3/FUPool.py         |  2 +-
 src/cpu/o3/FuncUnitConfig.py | 35 +++++++++++++++++++++++++++++++++++
 2 files changed, 36 insertions(+), 1 deletion(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py
index 4f07f9867..1d3afbc6b 100644
--- a/src/cpu/o3/FUPool.py
+++ b/src/cpu/o3/FUPool.py
@@ -37,4 +37,4 @@ class FUPool(SimObject):
 
 class DefaultFUPool(FUPool):
     FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
-               WritePort(), RdWrPort(), IprPort() ]
+               SIMD_Unit(), WritePort(), RdWrPort(), IprPort() ]
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index 954381f86..34c56163d 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2010 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
 # Copyright (c) 2006-2007 The Regents of The University of Michigan
 # All rights reserved.
 #
@@ -51,6 +63,29 @@ class FP_MultDiv(FUDesc):
                OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
     count = 2
 
+class SIMD_Unit(FUDesc):
+    opList = [ OpDesc(opClass='SimdAdd'),
+               OpDesc(opClass='SimdAddAcc'),
+               OpDesc(opClass='SimdAlu'),
+               OpDesc(opClass='SimdCmp'),
+               OpDesc(opClass='SimdCvt'),
+               OpDesc(opClass='SimdMisc'),
+               OpDesc(opClass='SimdMult'),
+               OpDesc(opClass='SimdMultAcc'),
+               OpDesc(opClass='SimdShift'),
+               OpDesc(opClass='SimdShiftAcc'),
+               OpDesc(opClass='SimdSqrt'),
+               OpDesc(opClass='SimdFloatAdd'),
+               OpDesc(opClass='SimdFloatAlu'),
+               OpDesc(opClass='SimdFloatCmp'),
+               OpDesc(opClass='SimdFloatCvt'),
+               OpDesc(opClass='SimdFloatDiv'),
+               OpDesc(opClass='SimdFloatMisc'),
+               OpDesc(opClass='SimdFloatMult'),
+               OpDesc(opClass='SimdFloatMultAcc'),
+               OpDesc(opClass='SimdFloatSqrt') ]
+    count = 4
+
 class ReadPort(FUDesc):
     opList = [ OpDesc(opClass='MemRead') ]
     count = 0
-- 
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