From 043709fdfab3b6c46f6ef95d1f642cd3c06ee20a Mon Sep 17 00:00:00 2001 From: Geoffrey Blake Date: Fri, 9 Mar 2012 09:59:27 -0500 Subject: CheckerCPU: Make CheckerCPU runtime selectable instead of compile selectable Enables the CheckerCPU to be selected at runtime with the --checker option from the configs/example/fs.py and configs/example/se.py configuration files. Also merges with the SE/FS changes. --- src/cpu/o3/O3CPU.py | 32 ++++++++++++++++---------------- src/cpu/o3/SConscript | 5 ++--- src/cpu/o3/checker_builder.cc | 1 + src/cpu/o3/commit_impl.hh | 12 +----------- src/cpu/o3/cpu.cc | 16 ++++------------ src/cpu/o3/cpu.hh | 3 --- src/cpu/o3/cpu_builder.cc | 1 - src/cpu/o3/dyn_inst_impl.hh | 10 +++++----- src/cpu/o3/fetch_impl.hh | 6 +----- src/cpu/o3/iew_impl.hh | 12 +++--------- src/cpu/o3/lsq_unit_impl.hh | 21 ++++++++------------- src/cpu/o3/thread_context.hh | 7 +------ src/cpu/o3/thread_context_impl.hh | 3 --- 13 files changed, 42 insertions(+), 87 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index acc7a9056..042c5e637 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -31,27 +31,12 @@ from m5.params import * from m5.proxy import * from BaseCPU import BaseCPU from FUPool import * - -if buildEnv['USE_CHECKER']: - from O3Checker import O3Checker +from O3Checker import O3Checker class DerivO3CPU(BaseCPU): type = 'DerivO3CPU' activity = Param.Unsigned(0, "Initial count") - if buildEnv['USE_CHECKER']: - # FIXME: Shouldn't need to derefernce Parent.workload - # Somewhere in the param parsing code - # src/python/m5/params.py is and error that - # has trouble converting the workload parameter properly. - checker = Param.BaseCPU(O3Checker(workload=Parent.workload[0], - exitOnError=False, - updateOnError=True, - warnOnlyOnLoadError=True), - "checker") - checker.itb = Parent.itb - checker.dtb = Parent.dtb - cachePorts = Param.Unsigned(200, "Cache Ports") decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay") @@ -145,3 +130,18 @@ class DerivO3CPU(BaseCPU): needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', "Enable TSO Memory model") + + def addCheckerCpu(self): + if buildEnv['TARGET_ISA'] in ['arm']: + from ArmTLB import ArmTLB + + self.checker = O3Checker(workload=self.workload, + exitOnError=False, + updateOnError=True, + warnOnlyOnLoadError=True) + self.checker.itb = ArmTLB(size = self.itb.size) + self.checker.dtb = ArmTLB(size = self.dtb.size) + + else: + print "ERROR: Checker only supported under ARM ISA!" + exit(1) diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index 8ed337c25..8ca32c898 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -78,6 +78,5 @@ if 'O3CPU' in env['CPU_MODELS']: 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) - if env['USE_CHECKER']: - SimObject('O3Checker.py') - Source('checker_builder.cc') + SimObject('O3Checker.py') + Source('checker_builder.cc') diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc index 72b50d104..757b1a87f 100644 --- a/src/cpu/o3/checker_builder.cc +++ b/src/cpu/o3/checker_builder.cc @@ -92,6 +92,7 @@ O3CheckerParams::create() temp = max_insts_all_threads; temp = max_loads_any_thread; temp = max_loads_all_threads; + temp++; Tick temp2 = progress_interval; params->progress_interval = 0; temp2++; diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index bb82c37a8..ce023e665 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -48,7 +48,7 @@ #include "base/loader/symtab.hh" #include "base/cp_annotate.hh" #include "config/the_isa.hh" -#include "config/use_checker.hh" +#include "cpu/checker/cpu.hh" #include "cpu/o3/commit.hh" #include "cpu/o3/thread_state.hh" #include "cpu/base.hh" @@ -63,10 +63,6 @@ #include "sim/faults.hh" #include "sim/full_system.hh" -#if USE_CHECKER -#include "cpu/checker/cpu.hh" -#endif - using namespace std; template @@ -737,11 +733,9 @@ DefaultCommit::handleInterrupt() assert(!thread[0]->inSyscall); thread[0]->inSyscall = true; -#if USE_CHECKER if (cpu->checker) { cpu->checker->handlePendingInt(); } -#endif // CPU will handle interrupt. cpu->processInterrupts(interrupt); @@ -1143,13 +1137,11 @@ DefaultCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) head_inst->setCompleted(); } -#if USE_CHECKER // Use checker prior to updating anything due to traps or PC // based events. if (cpu->checker) { cpu->checker->verify(head_inst); } -#endif if (inst_fault != NoFault) { DPRINTF(Commit, "Inst [sn:%lli] PC %s has a fault\n", @@ -1162,12 +1154,10 @@ DefaultCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) head_inst->setCompleted(); -#if USE_CHECKER if (cpu->checker) { // Need to check the instruction before its fault is processed cpu->checker->verify(head_inst); } -#endif assert(!thread[tid]->inSyscall); diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index bf2cc80e3..f68b500ea 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -45,7 +45,8 @@ #include "arch/kernel_stats.hh" #include "config/the_isa.hh" -#include "config/use_checker.hh" +#include "cpu/checker/cpu.hh" +#include "cpu/checker/thread_context.hh" #include "cpu/o3/cpu.hh" #include "cpu/o3/isa_specific.hh" #include "cpu/o3/thread_context.hh" @@ -63,11 +64,6 @@ #include "sim/stat_control.hh" #include "sim/system.hh" -#if USE_CHECKER -#include "cpu/checker/cpu.hh" -#include "cpu/checker/thread_context.hh" -#endif - #if THE_ISA == ALPHA_ISA #include "arch/alpha/osfpal.hh" #include "debug/Activity.hh" @@ -263,7 +259,6 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) _status = Idle; } -#if USE_CHECKER if (params->checker) { BaseCPU *temp_checker = params->checker; checker = dynamic_cast *>(temp_checker); @@ -272,7 +267,6 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) } else { checker = NULL; } -#endif // USE_CHECKER if (!FullSystem) { thread.resize(numThreads); @@ -438,12 +432,10 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) // If we're using a checker, then the TC should be the // CheckerThreadContext. -#if USE_CHECKER if (params->checker) { tc = new CheckerThreadContext >( o3_tc, this->checker); } -#endif o3_tc->cpu = (typename Impl::O3CPU *)(this); assert(o3_tc->cpu); @@ -1207,10 +1199,10 @@ FullO3CPU::switchOut() } _status = SwitchedOut; -#if USE_CHECKER + if (checker) checker->switchOut(); -#endif + if (tickEvent.scheduled()) tickEvent.squash(); } diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index f48c0f0f2..42e9f01f9 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -55,7 +55,6 @@ #include "arch/types.hh" #include "base/statistics.hh" #include "config/the_isa.hh" -#include "config/use_checker.hh" #include "cpu/o3/comm.hh" #include "cpu/o3/cpu_policy.hh" #include "cpu/o3/scoreboard.hh" @@ -720,13 +719,11 @@ class FullO3CPU : public BaseO3CPU /** The global sequence number counter. */ InstSeqNum globalSeqNum;//[Impl::MaxThreads]; -#if USE_CHECKER /** Pointer to the checker, which can dynamically verify * instruction results at run time. This can be set to NULL if it * is not being used. */ Checker *checker; -#endif /** Pointer to the system. */ System *system; diff --git a/src/cpu/o3/cpu_builder.cc b/src/cpu/o3/cpu_builder.cc index 296ad1793..71cebce05 100644 --- a/src/cpu/o3/cpu_builder.cc +++ b/src/cpu/o3/cpu_builder.cc @@ -30,7 +30,6 @@ #include -#include "config/use_checker.hh" #include "cpu/o3/cpu.hh" #include "cpu/o3/impl.hh" #include "params/DerivO3CPU.hh" diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh index ed1e374e8..2870d40fe 100644 --- a/src/cpu/o3/dyn_inst_impl.hh +++ b/src/cpu/o3/dyn_inst_impl.hh @@ -41,7 +41,6 @@ */ #include "base/cp_annotate.hh" -#include "config/use_checker.hh" #include "cpu/o3/dyn_inst.hh" #include "sim/full_system.hh" @@ -138,11 +137,12 @@ BaseO3DynInst::completeAcc(PacketPtr pkt) bool in_syscall = this->thread->inSyscall; this->thread->inSyscall = true; -#if USE_CHECKER - if (this->isStoreConditional()) { - this->reqToVerify->setExtraData(pkt->req->getExtraData()); + if (this->cpu->checker) { + if (this->isStoreConditional()) { + this->reqToVerify->setExtraData(pkt->req->getExtraData()); + } } -#endif + this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); this->thread->inSyscall = in_syscall; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 1271ea481..60b11080d 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -53,8 +53,8 @@ #include "arch/vtophys.hh" #include "base/types.hh" #include "config/the_isa.hh" -#include "config/use_checker.hh" #include "cpu/base.hh" +//#include "cpu/checker/cpu.hh" #include "cpu/o3/fetch.hh" #include "cpu/exetrace.hh" #include "debug/Activity.hh" @@ -68,10 +68,6 @@ #include "sim/full_system.hh" #include "sim/system.hh" -#if USE_CHECKER -#include "cpu/checker/cpu.hh" -#endif // USE_CHECKER - using namespace std; template diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 209ad317b..4aaa321c5 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -48,7 +48,7 @@ #include "arch/utility.hh" #include "config/the_isa.hh" -#include "config/use_checker.hh" +#include "cpu/checker/cpu.hh" #include "cpu/o3/fu_pool.hh" #include "cpu/o3/iew.hh" #include "cpu/timebuf.hh" @@ -57,10 +57,6 @@ #include "debug/IEW.hh" #include "params/DerivO3CPU.hh" -#if USE_CHECKER -#include "cpu/checker/cpu.hh" -#endif // USE_CHECKER - using namespace std; template @@ -299,12 +295,10 @@ DefaultIEW::initStage() ldstQueue.numFreeEntries(tid); } -// Initialize the checker's dcache port here -#if USE_CHECKER + // Initialize the checker's dcache port here if (cpu->checker) { cpu->checker->setDcachePort(&cpu->getDataPort()); - } -#endif + } cpu->activateStage(O3CPU::IEWIdx); } diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index facd88597..d0a630f6d 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -45,6 +45,7 @@ #include "arch/locked_mem.hh" #include "base/str.hh" #include "config/the_isa.hh" +#include "cpu/checker/cpu.hh" #include "cpu/o3/lsq.hh" #include "cpu/o3/lsq_unit.hh" #include "debug/Activity.hh" @@ -53,10 +54,6 @@ #include "mem/packet.hh" #include "mem/request.hh" -#if USE_CHECKER -#include "cpu/checker/cpu.hh" -#endif - template LSQUnit::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, LSQUnit *lsq_ptr) @@ -871,11 +868,12 @@ LSQUnit::writebackStores() inst->seqNum); WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); cpu->schedule(wb, curTick() + 1); -#if USE_CHECKER - // Make sure to set the LLSC data for verification - inst->reqToVerify->setExtraData(0); - inst->completeAcc(data_pkt); -#endif + if (cpu->checker) { + // Make sure to set the LLSC data for verification + // if checker is loaded + inst->reqToVerify->setExtraData(0); + inst->completeAcc(data_pkt); + } completeStore(storeWBIdx); incrStIdx(storeWBIdx); continue; @@ -1083,11 +1081,10 @@ LSQUnit::storePostSend(PacketPtr pkt) // only works so long as the checker doesn't try to // verify the value in memory for stores. storeQueue[storeWBIdx].inst->setCompleted(); -#if USE_CHECKER + if (cpu->checker) { cpu->checker->verify(storeQueue[storeWBIdx].inst); } -#endif } if (needsTSO) { @@ -1174,11 +1171,9 @@ LSQUnit::completeStore(int store_idx) // Tell the checker we've completed this instruction. Some stores // may get reported twice to the checker, but the checker can // handle that case. -#if USE_CHECKER if (cpu->checker) { cpu->checker->verify(storeQueue[store_idx].inst); } -#endif } template diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 8c32d1c05..ae76176ce 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -44,7 +44,6 @@ #define __CPU_O3_THREAD_CONTEXT_HH__ #include "config/the_isa.hh" -#include "config/use_checker.hh" #include "cpu/o3/isa_specific.hh" #include "cpu/thread_context.hh" @@ -84,9 +83,7 @@ class O3ThreadContext : public ThreadContext /** Returns a pointer to the DTB. */ TheISA::TLB *getDTBPtr() { return cpu->dtb; } -#if USE_CHECKER - BaseCPU *getCheckerCpuPtr() { return NULL; } -#endif + CheckerCPU *getCheckerCpuPtr() { return NULL; } Decoder *getDecoderPtr() { return &cpu->fetch.decoder; } @@ -194,9 +191,7 @@ class O3ThreadContext : public ThreadContext /** Sets this thread's PC state. */ virtual void pcState(const TheISA::PCState &val); -#if USE_CHECKER virtual void pcStateNoRecord(const TheISA::PCState &val); -#endif /** Reads this thread's PC. */ virtual Addr instAddr() diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index ecc40bd14..13bfe32df 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -44,7 +44,6 @@ #include "arch/kernel_stats.hh" #include "arch/registers.hh" #include "config/the_isa.hh" -#include "config/use_checker.hh" #include "cpu/o3/thread_context.hh" #include "cpu/quiesce_event.hh" #include "debug/O3CPU.hh" @@ -297,7 +296,6 @@ O3ThreadContext::pcState(const TheISA::PCState &val) } } -#if USE_CHECKER template void O3ThreadContext::pcStateNoRecord(const TheISA::PCState &val) @@ -309,7 +307,6 @@ O3ThreadContext::pcStateNoRecord(const TheISA::PCState &val) cpu->squashFromTC(thread->threadId()); } } -#endif template int -- cgit v1.2.3