From 9c582c7e144aef0bfc9d14bb4690d56d1688496a Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Tue, 17 Oct 2006 18:50:19 -0400 Subject: Fixes for uni-coherence in timing mode for FS. Still a bug in atomic uni-coherence in FS. src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Make CPU models handle coherence requests src/mem/cache/base_cache.cc: Properly signal coherence CSHRs src/mem/cache/coherence/uni_coherence.cc: Only deallocate once --HG-- extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99 --- src/cpu/o3/fetch_impl.hh | 5 ++++- src/cpu/o3/lsq_impl.hh | 9 ++++++++- 2 files changed, 12 insertions(+), 2 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 07d4ebb42..54b652813 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -80,7 +80,10 @@ template bool DefaultFetch::IcachePort::recvTiming(Packet *pkt) { - fetch->processCacheCompletion(pkt); + if (pkt->isResponse()) { + fetch->processCacheCompletion(pkt); + } + //else Snooped a coherence request, just return return true; } diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index 7b7d1eb8e..337ee0372 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -63,7 +63,14 @@ template bool LSQ::DcachePort::recvTiming(PacketPtr pkt) { - lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt); + if (pkt->isResponse()) { + lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt); + } + else { + //else it is a coherence request, maybe you need to do something + warn("Recieved a coherence request (Invalidate??), 03CPU doesn't" + "update LSQ for these\n"); + } return true; } -- cgit v1.2.3 From c2c48645c9b4f93cce8c1f653b6ef3e451829112 Mon Sep 17 00:00:00 2001 From: Lisa Hsu Date: Wed, 18 Oct 2006 17:59:11 -0400 Subject: only do this assert after you know you're not switched out or idle. --HG-- extra : convert_revision : 0cd0d31db44fe7e8e44bde90e1756873faca422f --- src/cpu/o3/cpu.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 4c9a8e91f..367508288 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -850,9 +850,6 @@ template void FullO3CPU::resume() { -#if FULL_SYSTEM - assert(system->getMemoryMode() == System::Timing); -#endif fetch.resume(); decode.resume(); rename.resume(); @@ -864,6 +861,10 @@ FullO3CPU::resume() if (_status == SwitchedOut || _status == Idle) return; +#if FULL_SYSTEM + assert(system->getMemoryMode() == System::Timing); +#endif + if (!tickEvent.scheduled()) tickEvent.schedule(curTick); _status = Running; -- cgit v1.2.3 From 210e73f2a298d494e4b15a3bf0523e58369c00d2 Mon Sep 17 00:00:00 2001 From: Ron Dreslinski Date: Thu, 19 Oct 2006 20:18:17 -0400 Subject: Small changes: ?? doesn't compile in warn statements Should have been false, where I had a true. src/cpu/o3/lsq_impl.hh: Apparently you can't have ?? in a warn statement (Something about trigraphs) src/mem/cache/cache_impl.hh: Forgot to signal atomic mode in snoopProbe --HG-- extra : convert_revision : c75cb76e193e852284564993440c8ea39e6de426 --- src/cpu/o3/lsq_impl.hh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index 337ee0372..317e23b14 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -68,7 +68,7 @@ LSQ::DcachePort::recvTiming(PacketPtr pkt) } else { //else it is a coherence request, maybe you need to do something - warn("Recieved a coherence request (Invalidate??), 03CPU doesn't" + warn("Recieved a coherence request (Invalidate?), 03CPU doesn't" "update LSQ for these\n"); } return true; -- cgit v1.2.3 From 7245d4530d0c8367fa7b1adadcb55e1e8bd466e7 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Thu, 19 Oct 2006 23:38:45 -0700 Subject: refactor code for the packet, get rid of packet_impl.hh and call it packet_access.hh and fix the #includes so things compile right. --HG-- extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724 --- src/cpu/o3/fetch.hh | 2 +- src/cpu/o3/lsq_unit.hh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 280bf0e71..5555bff85 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -36,7 +36,7 @@ #include "base/statistics.hh" #include "base/timebuf.hh" #include "cpu/pc_event.hh" -#include "mem/packet_impl.hh" +#include "mem/packet.hh" #include "mem/port.hh" #include "sim/eventq.hh" diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 11a02e7c7..0aac466b5 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -40,7 +40,7 @@ #include "config/full_system.hh" #include "base/hashmap.hh" #include "cpu/inst_seq.hh" -#include "mem/packet_impl.hh" +#include "mem/packet.hh" #include "mem/port.hh" /** -- cgit v1.2.3 From a4c6f0d69eda5d23b12576080d532ddf768fbdbe Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 20 Oct 2006 00:10:12 -0700 Subject: Use PacketPtr everywhere --HG-- extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711 --- src/cpu/o3/alpha/dyn_inst.hh | 2 +- src/cpu/o3/alpha/dyn_inst_impl.hh | 2 +- src/cpu/o3/fetch_impl.hh | 2 +- src/cpu/o3/lsq_unit.hh | 2 +- src/cpu/o3/lsq_unit_impl.hh | 2 +- src/cpu/o3/mips/dyn_inst.hh | 2 +- src/cpu/o3/mips/dyn_inst_impl.hh | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index 9dee610b6..294aadde8 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -86,7 +86,7 @@ class AlphaDynInst : public BaseDynInst Fault initiateAcc(); /** Completes the access. Only valid for memory operations. */ - Fault completeAcc(Packet *pkt); + Fault completeAcc(PacketPtr pkt); private: /** Initializes variables. */ diff --git a/src/cpu/o3/alpha/dyn_inst_impl.hh b/src/cpu/o3/alpha/dyn_inst_impl.hh index 2d1b4b309..b273a7b9b 100644 --- a/src/cpu/o3/alpha/dyn_inst_impl.hh +++ b/src/cpu/o3/alpha/dyn_inst_impl.hh @@ -100,7 +100,7 @@ AlphaDynInst::initiateAcc() template Fault -AlphaDynInst::completeAcc(Packet *pkt) +AlphaDynInst::completeAcc(PacketPtr pkt) { this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 54b652813..da75bfecf 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -78,7 +78,7 @@ DefaultFetch::IcachePort::recvStatusChange(Status status) template bool -DefaultFetch::IcachePort::recvTiming(Packet *pkt) +DefaultFetch::IcachePort::recvTiming(PacketPtr pkt) { if (pkt->isResponse()) { fetch->processCacheCompletion(pkt); diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 0aac466b5..1b207fdbc 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -219,7 +219,7 @@ class LSQUnit { void writeback(DynInstPtr &inst, PacketPtr pkt); /** Handles completing the send of a store to memory. */ - void storePostSend(Packet *pkt); + void storePostSend(PacketPtr pkt); /** Completes the store at the specified index. */ void completeStore(int store_idx); diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 3f9db912f..d940d7cb3 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -763,7 +763,7 @@ LSQUnit::squash(const InstSeqNum &squashed_num) template void -LSQUnit::storePostSend(Packet *pkt) +LSQUnit::storePostSend(PacketPtr pkt) { if (isStalled() && storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh index 06bdfcec4..aa30bfa1e 100755 --- a/src/cpu/o3/mips/dyn_inst.hh +++ b/src/cpu/o3/mips/dyn_inst.hh @@ -87,7 +87,7 @@ class MipsDynInst : public BaseDynInst Fault initiateAcc(); /** Completes the access. Only valid for memory operations. */ - Fault completeAcc(Packet *pkt); + Fault completeAcc(PacketPtr pkt); private: /** Initializes variables. */ diff --git a/src/cpu/o3/mips/dyn_inst_impl.hh b/src/cpu/o3/mips/dyn_inst_impl.hh index 57dec1ccf..5bc01b9b3 100755 --- a/src/cpu/o3/mips/dyn_inst_impl.hh +++ b/src/cpu/o3/mips/dyn_inst_impl.hh @@ -100,7 +100,7 @@ MipsDynInst::initiateAcc() template Fault -MipsDynInst::completeAcc(Packet *pkt) +MipsDynInst::completeAcc(PacketPtr pkt) { this->fault = this->staticInst->completeAcc(pkt, this, this->traceData); -- cgit v1.2.3