From 0cba96ba6a5d7a4dab2a63b14149c49dfbfbb3bc Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sat, 26 May 2012 13:44:46 -0700
Subject: CPU: Merge the predecoder and decoder.

These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.

--HG--
rename : src/arch/x86/predecoder_tables.cc => src/arch/x86/decoder_tables.cc
---
 src/cpu/o3/fetch.hh          |  6 +-----
 src/cpu/o3/fetch_impl.hh     | 28 ++++++++++++++--------------
 src/cpu/o3/thread_context.hh |  6 +++++-
 3 files changed, 20 insertions(+), 20 deletions(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh
index 474834889..6bf5f4588 100644
--- a/src/cpu/o3/fetch.hh
+++ b/src/cpu/o3/fetch.hh
@@ -45,7 +45,6 @@
 #define __CPU_O3_FETCH_HH__
 
 #include "arch/decoder.hh"
-#include "arch/predecoder.hh"
 #include "arch/utility.hh"
 #include "base/statistics.hh"
 #include "config/the_isa.hh"
@@ -340,7 +339,7 @@ class DefaultFetch
     }
 
     /** The decoder. */
-    TheISA::Decoder decoder;
+    TheISA::Decoder *decoder[Impl::MaxThreads];
 
   private:
     DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
@@ -398,9 +397,6 @@ class DefaultFetch
     /** BPredUnit. */
     BPredUnit branchPred;
 
-    /** Predecoder. */
-    TheISA::Predecoder predecoder;
-
     TheISA::PCState pc[Impl::MaxThreads];
 
     Addr fetchOffset[Impl::MaxThreads];
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index f4ce77f22..b6eb25c08 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -73,7 +73,6 @@ template<class Impl>
 DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
     : cpu(_cpu),
       branchPred(params),
-      predecoder(NULL),
       numInst(0),
       decodeToFetchDelay(params->decodeToFetchDelay),
       renameToFetchDelay(params->renameToFetchDelay),
@@ -132,6 +131,9 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
 
     // Get the size of an instruction.
     instSize = sizeof(TheISA::MachInst);
+
+    for (int i = 0; i < Impl::MaxThreads; i++)
+        decoder[i] = new TheISA::Decoder(NULL);
 }
 
 template <class Impl>
@@ -660,7 +662,7 @@ DefaultFetch<Impl>::finishTranslation(Fault fault, RequestPtr mem_req)
         DPRINTF(Fetch, "[tid:%i]: Translation faulted, building noop.\n", tid);
         // We will use a nop in ordier to carry the fault.
         DynInstPtr instruction = buildInst(tid,
-                decoder.decode(TheISA::NoopMachInst, fetchPC.instAddr()),
+                decoder[tid]->decode(TheISA::NoopMachInst, fetchPC.instAddr()),
                 NULL, fetchPC, fetchPC, false);
 
         instruction->setPredTarg(fetchPC);
@@ -693,7 +695,7 @@ DefaultFetch<Impl>::doSquash(const TheISA::PCState &newPC,
         macroop[tid] = squashInst->macroop;
     else
         macroop[tid] = NULL;
-    predecoder.reset();
+    decoder[tid]->reset();
 
     // Clear the icache miss if it's outstanding.
     if (fetchStatus[tid] == IcacheWaitResponse) {
@@ -1193,8 +1195,9 @@ DefaultFetch<Impl>::fetch(bool &status_change)
 
         // We need to process more memory if we aren't going to get a
         // StaticInst from the rom, the current macroop, or what's already
-        // in the predecoder.
-        bool needMem = !inRom && !curMacroop && !predecoder.extMachInstReady();
+        // in the decoder.
+        bool needMem = !inRom && !curMacroop &&
+            !decoder[tid]->instReady();
         fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
         Addr block_PC = icacheBlockAlignPC(fetchAddr);
 
@@ -1222,10 +1225,10 @@ DefaultFetch<Impl>::fetch(bool &status_change)
             }
             MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
 
-            predecoder.setTC(cpu->thread[tid]->getTC());
-            predecoder.moreBytes(thisPC, fetchAddr, inst);
+            decoder[tid]->setTC(cpu->thread[tid]->getTC());
+            decoder[tid]->moreBytes(thisPC, fetchAddr, inst);
 
-            if (predecoder.needMoreBytes()) {
+            if (decoder[tid]->needMoreBytes()) {
                 blkOffset++;
                 fetchAddr += instSize;
                 pcOffset += instSize;
@@ -1236,11 +1239,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
         // the memory we've processed so far.
         do {
             if (!(curMacroop || inRom)) {
-                if (predecoder.extMachInstReady()) {
-                    ExtMachInst extMachInst =
-                        predecoder.getExtMachInst(thisPC);
-                    staticInst =
-                        decoder.decode(extMachInst, thisPC.instAddr());
+                if (decoder[tid]->instReady()) {
+                    staticInst = decoder[tid]->decode(thisPC);
 
                     // Increment stat of fetched instructions.
                     ++fetchedInsts;
@@ -1311,7 +1311,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                 status_change = true;
                 break;
             }
-        } while ((curMacroop || predecoder.extMachInstReady()) &&
+        } while ((curMacroop || decoder[tid]->instReady()) &&
                  numInst < fetchWidth);
     }
 
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index b4108e25c..5c236ee0c 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -85,7 +85,11 @@ class O3ThreadContext : public ThreadContext
 
     CheckerCPU *getCheckerCpuPtr() { return NULL; }
 
-    TheISA::Decoder *getDecoderPtr() { return &cpu->fetch.decoder; }
+    TheISA::Decoder *
+    getDecoderPtr()
+    {
+        return cpu->fetch.decoder[thread->threadId()];
+    }
 
     /** Returns a pointer to this CPU. */
     virtual BaseCPU *getCpuPtr() { return cpu; }
-- 
cgit v1.2.3