From 101d6e356c630e9e0d48c0b3188807b8e5818c37 Mon Sep 17 00:00:00 2001 From: Iru Cai Date: Fri, 12 Apr 2019 01:22:41 +0800 Subject: keep time to expose as original scheme when inst->needPostFetch() because when inst->needPostFetch(), it means that the spec load is already issued this also fixes the mysterious bug caused by the IFT code --- src/cpu/o3/lsq_unit_impl.hh | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 7ac85654e..a8ec0333f 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -1056,18 +1056,15 @@ LSQUnit::updateVisibleState() } else { /* set taint for dst registers */ inst->taintDestRegs(true); - inst->isTainted = true; /* if the load depends on tainted registers, set readyToExpose to false, otherwise set it to true */ - if (inst->srcTainted()) { + bool doSpecLoad = inst->needPostFetch() || inst->srcTainted(); + if (doSpecLoad) { DPRINTF(LSQUnit, "load inst [sn:%lli] %s not safe, set readyToExpose to false\n", inst->seqNum, inst->pcState()); inst->readyToExpose(false); } else { DPRINTF(LSQUnit, "load inst [sn:%lli] %s is an unsafe speculated load, but source registers are not tainted.\n", inst->seqNum, inst->pcState()); - if (!inst->readyToExpose() && inst->needPostFetch()) { - ++loadsToVLD; - } inst->readyToExpose(true); } } -- cgit v1.2.3