From 25884a87733cd35ef6613aaef9a8a08194267552 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:20 -0700 Subject: Registers: Get rid of the float register width parameter. --- src/cpu/o3/cpu.cc | 52 ++----------------------------- src/cpu/o3/cpu.hh | 16 ++-------- src/cpu/o3/dyn_inst.hh | 25 --------------- src/cpu/o3/regfile.hh | 62 ------------------------------------- src/cpu/o3/thread_context.hh | 8 ----- src/cpu/o3/thread_context_impl.hh | 64 ++------------------------------------- 6 files changed, 6 insertions(+), 221 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 2f8869b6f..394efe16a 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1213,13 +1213,6 @@ FullO3CPU::readIntReg(int reg_idx) return regFile.readIntReg(reg_idx); } -template -FloatReg -FullO3CPU::readFloatReg(int reg_idx, int width) -{ - return regFile.readFloatReg(reg_idx, width); -} - template FloatReg FullO3CPU::readFloatReg(int reg_idx) @@ -1227,13 +1220,6 @@ FullO3CPU::readFloatReg(int reg_idx) return regFile.readFloatReg(reg_idx); } -template -FloatRegBits -FullO3CPU::readFloatRegBits(int reg_idx, int width) -{ - return regFile.readFloatRegBits(reg_idx, width); -} - template FloatRegBits FullO3CPU::readFloatRegBits(int reg_idx) @@ -1248,13 +1234,6 @@ FullO3CPU::setIntReg(int reg_idx, uint64_t val) regFile.setIntReg(reg_idx, val); } -template -void -FullO3CPU::setFloatReg(int reg_idx, FloatReg val, int width) -{ - regFile.setFloatReg(reg_idx, val, width); -} - template void FullO3CPU::setFloatReg(int reg_idx, FloatReg val) @@ -1262,13 +1241,6 @@ FullO3CPU::setFloatReg(int reg_idx, FloatReg val) regFile.setFloatReg(reg_idx, val); } -template -void -FullO3CPU::setFloatRegBits(int reg_idx, FloatRegBits val, int width) -{ - regFile.setFloatRegBits(reg_idx, val, width); -} - template void FullO3CPU::setFloatRegBits(int reg_idx, FloatRegBits val) @@ -1287,7 +1259,7 @@ FullO3CPU::readArchIntReg(int reg_idx, ThreadID tid) template float -FullO3CPU::readArchFloatRegSingle(int reg_idx, ThreadID tid) +FullO3CPU::readArchFloatReg(int reg_idx, ThreadID tid) { int idx = reg_idx + TheISA::NumIntRegs; PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); @@ -1295,16 +1267,6 @@ FullO3CPU::readArchFloatRegSingle(int reg_idx, ThreadID tid) return regFile.readFloatReg(phys_reg); } -template -double -FullO3CPU::readArchFloatRegDouble(int reg_idx, ThreadID tid) -{ - int idx = reg_idx + TheISA::NumIntRegs; - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); - - return regFile.readFloatReg(phys_reg, 64); -} - template uint64_t FullO3CPU::readArchFloatRegInt(int reg_idx, ThreadID tid) @@ -1326,7 +1288,7 @@ FullO3CPU::setArchIntReg(int reg_idx, uint64_t val, ThreadID tid) template void -FullO3CPU::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid) +FullO3CPU::setArchFloatReg(int reg_idx, float val, ThreadID tid) { int idx = reg_idx + TheISA::NumIntRegs; PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); @@ -1334,16 +1296,6 @@ FullO3CPU::setArchFloatRegSingle(int reg_idx, float val, ThreadID tid) regFile.setFloatReg(phys_reg, val); } -template -void -FullO3CPU::setArchFloatRegDouble(int reg_idx, double val, ThreadID tid) -{ - int idx = reg_idx + TheISA::NumIntRegs; - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); - - regFile.setFloatReg(phys_reg, val, 64); -} - template void FullO3CPU::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid) diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 1289785dc..c077b2493 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -435,27 +435,17 @@ class FullO3CPU : public BaseO3CPU TheISA::FloatReg readFloatReg(int reg_idx); - TheISA::FloatReg readFloatReg(int reg_idx, int width); - TheISA::FloatRegBits readFloatRegBits(int reg_idx); - TheISA::FloatRegBits readFloatRegBits(int reg_idx, int width); - void setIntReg(int reg_idx, uint64_t val); void setFloatReg(int reg_idx, TheISA::FloatReg val); - void setFloatReg(int reg_idx, TheISA::FloatReg val, int width); - void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val); - void setFloatRegBits(int reg_idx, TheISA::FloatRegBits val, int width); - uint64_t readArchIntReg(int reg_idx, ThreadID tid); - float readArchFloatRegSingle(int reg_idx, ThreadID tid); - - double readArchFloatRegDouble(int reg_idx, ThreadID tid); + float readArchFloatReg(int reg_idx, ThreadID tid); uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid); @@ -466,9 +456,7 @@ class FullO3CPU : public BaseO3CPU */ void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid); - void setArchFloatRegSingle(int reg_idx, float val, ThreadID tid); - - void setArchFloatRegDouble(int reg_idx, double val, ThreadID tid); + void setArchFloatReg(int reg_idx, float val, ThreadID tid); void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid); diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh index 292547b6b..3ef42e91f 100644 --- a/src/cpu/o3/dyn_inst.hh +++ b/src/cpu/o3/dyn_inst.hh @@ -196,22 +196,11 @@ class BaseO3DynInst : public BaseDynInst return this->cpu->readIntReg(this->_srcRegIdx[idx]); } - FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) - { - return this->cpu->readFloatReg(this->_srcRegIdx[idx], width); - } - FloatReg readFloatRegOperand(const StaticInst *si, int idx) { return this->cpu->readFloatReg(this->_srcRegIdx[idx]); } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, - int width) - { - return this->cpu->readFloatRegBits(this->_srcRegIdx[idx], width); - } - FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]); @@ -226,26 +215,12 @@ class BaseO3DynInst : public BaseDynInst BaseDynInst::setIntRegOperand(si, idx, val); } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, - int width) - { - this->cpu->setFloatReg(this->_destRegIdx[idx], val, width); - BaseDynInst::setFloatRegOperand(si, idx, val, width); - } - void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { this->cpu->setFloatReg(this->_destRegIdx[idx], val); BaseDynInst::setFloatRegOperand(si, idx, val); } - void setFloatRegOperandBits(const StaticInst *si, int idx, - FloatRegBits val, int width) - { - this->cpu->setFloatRegBits(this->_destRegIdx[idx], val, width); - BaseDynInst::setFloatRegOperandBits(si, idx, val); - } - void setFloatRegOperandBits(const StaticInst *si, int idx, FloatRegBits val) { diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index e7b20e4a9..44c349ef4 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -93,21 +93,6 @@ class PhysRegFile return intRegFile[reg_idx]; } - FloatReg readFloatReg(PhysRegIndex reg_idx, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); - - FloatReg floatReg = floatRegFile[reg_idx].d; - - DPRINTF(IEW, "RegFile: Access to %d byte float register %i, has " - "data %#x\n", int(reg_idx), floatRegFile[reg_idx].q); - - return floatReg; - } - /** Reads a floating point register (double precision). */ FloatReg readFloatReg(PhysRegIndex reg_idx) { @@ -124,22 +109,6 @@ class PhysRegFile return floatReg; } - /** Reads a floating point register as an integer. */ - FloatRegBits readFloatRegBits(PhysRegIndex reg_idx, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs + numPhysicalIntRegs); - - FloatRegBits floatRegBits = floatRegFile[reg_idx].q; - - DPRINTF(IEW, "RegFile: Access to float register %i as int, " - "has data %#x\n", int(reg_idx), (uint64_t)floatRegBits); - - return floatRegBits; - } - FloatRegBits readFloatRegBits(PhysRegIndex reg_idx) { // Remove the base Float reg dependency. @@ -167,23 +136,6 @@ class PhysRegFile intRegFile[reg_idx] = val; } - /** Sets a single precision floating point register to the given value. */ - void setFloatReg(PhysRegIndex reg_idx, FloatReg val, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs); - - DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", - int(reg_idx), (uint64_t)val); - -#if THE_ISA == ALPHA_ISA - if (reg_idx != TheISA::ZeroReg) -#endif - floatRegFile[reg_idx].d = val; - } - /** Sets a double precision floating point register to the given value. */ void setFloatReg(PhysRegIndex reg_idx, FloatReg val) { @@ -201,20 +153,6 @@ class PhysRegFile floatRegFile[reg_idx].d = val; } - /** Sets a floating point register to the given integer value. */ - void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val, int width) - { - // Remove the base Float reg dependency. - reg_idx = reg_idx - numPhysicalIntRegs; - - assert(reg_idx < numPhysicalFloatRegs); - - DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n", - int(reg_idx), (uint64_t)val); - - floatRegFile[reg_idx].q = val; - } - void setFloatRegBits(PhysRegIndex reg_idx, FloatRegBits val) { // Remove the base Float reg dependency. diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index a3f1ce58f..ed5c6ac20 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -167,23 +167,15 @@ class O3ThreadContext : public ThreadContext /** Reads an integer register. */ virtual uint64_t readIntReg(int reg_idx); - virtual FloatReg readFloatReg(int reg_idx, int width); - virtual FloatReg readFloatReg(int reg_idx); - virtual FloatRegBits readFloatRegBits(int reg_idx, int width); - virtual FloatRegBits readFloatRegBits(int reg_idx); /** Sets an integer register to a value. */ virtual void setIntReg(int reg_idx, uint64_t val); - virtual void setFloatReg(int reg_idx, FloatReg val, int width); - virtual void setFloatReg(int reg_idx, FloatReg val); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val, int width); - virtual void setFloatRegBits(int reg_idx, FloatRegBits val); /** Reads this thread's PC. */ diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 6527f5d06..0b5eddc73 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -276,37 +276,12 @@ O3ThreadContext::readIntReg(int reg_idx) return cpu->readArchIntReg(reg_idx, thread->threadId()); } -template -TheISA::FloatReg -O3ThreadContext::readFloatReg(int reg_idx, int width) -{ - reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); - switch(width) { - case 32: - return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); - case 64: - return cpu->readArchFloatRegDouble(reg_idx, thread->threadId()); - default: - panic("Unsupported width!"); - return 0; - } -} - template TheISA::FloatReg O3ThreadContext::readFloatReg(int reg_idx) { reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); - return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); -} - -template -TheISA::FloatRegBits -O3ThreadContext::readFloatRegBits(int reg_idx, int width) -{ - DPRINTF(Fault, "Reading floatint register through the TC!\n"); - reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); - return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); + return cpu->readArchFloatReg(reg_idx, thread->threadId()); } template @@ -330,53 +305,18 @@ O3ThreadContext::setIntReg(int reg_idx, uint64_t val) } } -template -void -O3ThreadContext::setFloatReg(int reg_idx, FloatReg val, int width) -{ - reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); - switch(width) { - case 32: - cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); - break; - case 64: - cpu->setArchFloatRegDouble(reg_idx, val, thread->threadId()); - break; - } - - // Squash if we're not already in a state update mode. - if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->threadId()); - } -} - template void O3ThreadContext::setFloatReg(int reg_idx, FloatReg val) { reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); - cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); + cpu->setArchFloatReg(reg_idx, val, thread->threadId()); if (!thread->trapPending && !thread->inSyscall) { cpu->squashFromTC(thread->threadId()); } } -template -void -O3ThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val, - int width) -{ - DPRINTF(Fault, "Setting floatint register through the TC!\n"); - reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); - cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); - - // Squash if we're not already in a state update mode. - if (!thread->trapPending && !thread->inSyscall) { - cpu->squashFromTC(thread->threadId()); - } -} - template void O3ThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val) -- cgit v1.2.3