From c96160cef541b1b4b3e58bf0c56612ef17250e46 Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Wed, 29 Nov 2006 16:07:55 -0500
Subject: Change the connecting of the physPort and virtPort to the memory
 object below the CPU to happen every time activateContext is called.  The
 overhead is probably a little higher than necessary, but allows these
 connections to properly be made when there are CPUs that are inactive until
 they are switched in.

Right now this introduces a minor memory leak as old physPorts and virtPorts are not deleted when new ones are created.  A flyspray task has been created for this issue.  It can not be resolved until we determine how the bus will handle giving out ID's to functional ports that may be deleted.

src/cpu/o3/cpu.cc:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
    Change the setup of the physPort and virtPort to instead happen every time the CPU has a context activated.  This is a little high overhead, but keeps it working correctly when the CPU does not have a physical memory attached to it until it switches in (like the case of switch CPUs).
src/cpu/o3/thread_context.hh:
    Change function from being called at init() to just being called whenever the memory ports need to be connected.
src/cpu/o3/thread_context_impl.hh:
    Update this to not delete the port if it's the same as the virtPort.
src/cpu/thread_context.hh:
    Change function from being called at init() to whenever the memory ports need to be connected.
src/cpu/thread_state.cc:
    Instead of initializing the ports, simply connect them, deleting any old ports that might exist.  This allows these functions to be called multiple times.
src/cpu/thread_state.hh:
    Ports are no longer initialized, but rather connected at context activation time.

--HG--
extra : convert_revision : e399ce5dfbd6ad658c953a7c9c7b69b89a70219e
---
 src/cpu/o3/cpu.cc                 | 8 ++++++--
 src/cpu/o3/thread_context.hh      | 2 +-
 src/cpu/o3/thread_context_impl.hh | 6 ++++--
 3 files changed, 11 insertions(+), 5 deletions(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 3dc353a9f..a5a00015f 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -497,8 +497,6 @@ FullO3CPU<Impl>::init()
         }
 
 #if FULL_SYSTEM
-        src_tc->init();
-
         TheISA::initCPU(src_tc, src_tc->readCpuId());
 #endif
     }
@@ -554,6 +552,12 @@ template <class Impl>
 void
 FullO3CPU<Impl>::activateContext(int tid, int delay)
 {
+#if FULL_SYSTEM
+    // Connect the ThreadContext's memory ports (Functional/Virtual
+    // Ports)
+    threadContexts[tid]->connectMemPorts();
+#endif
+
     // Needs to set each stage to running as well.
     if (delay){
         DPRINTF(O3CPU, "[tid:%i]: Scheduling thread context to activate "
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 031f36480..390569c3d 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -92,7 +92,7 @@ class O3ThreadContext : public ThreadContext
 
     void delVirtPort(VirtualPort *vp);
 
-    virtual void init() { thread->init(); }
+    virtual void connectMemPorts() { thread->connectMemPorts(); }
 #else
     virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
 
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 0180756e3..afebf294f 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -101,8 +101,10 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::delVirtPort(VirtualPort *vp)
 {
-    delete vp->getPeer();
-    delete vp;
+    if (vp != thread->getVirtPort()) {
+        delete vp->getPeer();
+        delete vp;
+    }
 }
 #endif
 
-- 
cgit v1.2.3


From c0f21b09c81e5562a916f7cb562a7df7f7709f4a Mon Sep 17 00:00:00 2001
From: Kevin Lim <ktlim@umich.edu>
Date: Sat, 2 Dec 2006 13:33:46 -0500
Subject: Fixes for MIPS_SE compiling.  Regressions seem to work, but Korey
 should make sure these changes (commit especially) work okay.

src/cpu/o3/commit_impl.hh:
src/cpu/o3/fetch_impl.hh:
    Fixes for MIPS_SE compile.

--HG--
extra : convert_revision : fde9616f8e72b397c5ca965774172372cff53790
---
 src/cpu/o3/commit_impl.hh | 1 +
 src/cpu/o3/fetch_impl.hh  | 2 ++
 2 files changed, 3 insertions(+)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index e72679710..43305f962 100644
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -748,6 +748,7 @@ DefaultCommit<Impl>::commit()
                 }
             } else {
                 bdelay_done_seq_num = squashed_inst;
+                squash_bdelay_slot = true;
             }
 #endif
 
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 63d22b293..4c378e18b 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -1139,6 +1139,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
             ext_inst = TheISA::makeExtMI(inst, fetch_PC);
 #elif THE_ISA == SPARC_ISA
             ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
+#elif THE_ISA == MIPS_ISA
+            ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC());
 #endif
 
             // Create a new DynInst from the instruction fetched.
-- 
cgit v1.2.3