From 32daf6fc3fd34af0023ae74c2a1f8dd597f87242 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 8 Jul 2009 23:02:20 -0700 Subject: Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU. --- src/cpu/o3/cpu.cc | 8 ++++---- src/cpu/o3/cpu.hh | 6 ++++-- src/cpu/o3/regfile.hh | 33 --------------------------------- src/cpu/o3/rename_impl.hh | 6 +++--- src/cpu/o3/thread_context.hh | 3 +++ src/cpu/o3/thread_context_impl.hh | 34 ++++++++++++++++++++++++---------- 6 files changed, 38 insertions(+), 52 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 621b6c1b9..2f8869b6f 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -1180,14 +1180,14 @@ template TheISA::MiscReg FullO3CPU::readMiscRegNoEffect(int misc_reg, ThreadID tid) { - return this->regFile.readMiscRegNoEffect(misc_reg, tid); + return this->isa[tid].readMiscRegNoEffect(misc_reg); } template TheISA::MiscReg FullO3CPU::readMiscReg(int misc_reg, ThreadID tid) { - return this->regFile.readMiscReg(misc_reg, tid); + return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); } template @@ -1195,7 +1195,7 @@ void FullO3CPU::setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { - this->regFile.setMiscRegNoEffect(misc_reg, val, tid); + this->isa[tid].setMiscRegNoEffect(misc_reg, val); } template @@ -1203,7 +1203,7 @@ void FullO3CPU::setMiscReg(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { - this->regFile.setMiscReg(misc_reg, val, tid); + this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); } template diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 5cf27df75..1289785dc 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -395,11 +395,11 @@ class FullO3CPU : public BaseO3CPU /** Get instruction asid. */ int getInstAsid(ThreadID tid) - { return regFile.miscRegs[tid].getInstAsid(); } + { return isa[tid].instAsid(); } /** Get data asid. */ int getDataAsid(ThreadID tid) - { return regFile.miscRegs[tid].getDataAsid(); } + { return isa[tid].dataAsid(); } #else /** Get instruction asid. */ int getInstAsid(ThreadID tid) @@ -603,6 +603,8 @@ class FullO3CPU : public BaseO3CPU /** Integer Register Scoreboard */ Scoreboard scoreboard; + TheISA::ISA isa[Impl::MaxThreads]; + public: /** Enum to give each stage a specific index, so when calling * activateStage() or deactivateStage(), they can specify which stage diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 07f8d487b..e7b20e4a9 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -57,8 +57,6 @@ class PhysRegFile typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; - typedef TheISA::MiscRegFile MiscRegFile; - typedef TheISA::MiscReg MiscReg; typedef union { FloatReg d; @@ -230,30 +228,6 @@ class PhysRegFile floatRegFile[reg_idx].q = val; } - MiscReg - readMiscRegNoEffect(int misc_reg, ThreadID tid) - { - return miscRegs[tid].readRegNoEffect(misc_reg); - } - - MiscReg - readMiscReg(int misc_reg, ThreadID tid) - { - return miscRegs[tid].readReg(misc_reg, cpu->tcBase(tid)); - } - - void - setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid) - { - miscRegs[tid].setRegNoEffect(misc_reg, val); - } - - void - setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid) - { - miscRegs[tid].setReg(misc_reg, val, cpu->tcBase(tid)); - } - public: /** (signed) integer register file. */ IntReg *intRegFile; @@ -261,9 +235,6 @@ class PhysRegFile /** Floating point register file. */ PhysFloatReg *floatRegFile; - /** Miscellaneous register file. */ - MiscRegFile miscRegs[Impl::MaxThreads]; - #if FULL_SYSTEM private: int intrflag; // interrupt flag @@ -289,10 +260,6 @@ PhysRegFile::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs, intRegFile = new IntReg[numPhysicalIntRegs]; floatRegFile = new PhysFloatReg[numPhysicalFloatRegs]; - for (int i = 0; i < Impl::MaxThreads; ++i) { - miscRegs[i].clear(); - } - memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs); memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs); } diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 2bca6f81c..dd480f81c 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -959,11 +959,11 @@ DefaultRename::renameSrcRegs(DynInstPtr &inst, ThreadID tid) RegIndex src_reg = inst->srcRegIdx(src_idx); RegIndex flat_src_reg = src_reg; if (src_reg < TheISA::FP_Base_DepTag) { - flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg); + flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg); } else if (src_reg < TheISA::Ctrl_Base_DepTag) { src_reg = src_reg - TheISA::FP_Base_DepTag; - flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg); + flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg); flat_src_reg += TheISA::NumIntRegs; } else { flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs; @@ -1009,7 +1009,7 @@ DefaultRename::renameDestRegs(DynInstPtr &inst, ThreadID tid) RegIndex flat_dest_reg = dest_reg; if (dest_reg < TheISA::FP_Base_DepTag) { // Integer registers are flattened. - flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg); + flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg); DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg); } else { // Floating point and Miscellaneous registers need their indexes diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index b10305d5d..a3f1ce58f 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -226,6 +226,9 @@ class O3ThreadContext : public ThreadContext * write might have as defined by the architecture. */ virtual void setMiscReg(int misc_reg, const MiscReg &val); + virtual int flattenIntIndex(int reg); + virtual int flattenFloatIndex(int reg); + /** Returns the number of consecutive store conditional failures. */ // @todo: Figure out where these store cond failures should go. virtual unsigned readStCondFailures() diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index bce334dc4..6527f5d06 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -272,7 +272,7 @@ template uint64_t O3ThreadContext::readIntReg(int reg_idx) { - reg_idx = TheISA::flattenIntIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); return cpu->readArchIntReg(reg_idx, thread->threadId()); } @@ -280,7 +280,7 @@ template TheISA::FloatReg O3ThreadContext::readFloatReg(int reg_idx, int width) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); switch(width) { case 32: return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); @@ -296,7 +296,7 @@ template TheISA::FloatReg O3ThreadContext::readFloatReg(int reg_idx) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); return cpu->readArchFloatRegSingle(reg_idx, thread->threadId()); } @@ -305,7 +305,7 @@ TheISA::FloatRegBits O3ThreadContext::readFloatRegBits(int reg_idx, int width) { DPRINTF(Fault, "Reading floatint register through the TC!\n"); - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); } @@ -313,7 +313,7 @@ template TheISA::FloatRegBits O3ThreadContext::readFloatRegBits(int reg_idx) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); } @@ -321,7 +321,7 @@ template void O3ThreadContext::setIntReg(int reg_idx, uint64_t val) { - reg_idx = TheISA::flattenIntIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); cpu->setArchIntReg(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. @@ -334,7 +334,7 @@ template void O3ThreadContext::setFloatReg(int reg_idx, FloatReg val, int width) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); switch(width) { case 32: cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); @@ -354,7 +354,7 @@ template void O3ThreadContext::setFloatReg(int reg_idx, FloatReg val) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId()); if (!thread->trapPending && !thread->inSyscall) { @@ -368,7 +368,7 @@ O3ThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { DPRINTF(Fault, "Setting floatint register through the TC!\n"); - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. @@ -381,7 +381,7 @@ template void O3ThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val) { - reg_idx = TheISA::flattenFloatIndex(this, reg_idx); + reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); // Squash if we're not already in a state update mode. @@ -438,6 +438,20 @@ O3ThreadContext::setNextMicroPC(uint64_t val) } } +template +int +O3ThreadContext::flattenIntIndex(int reg) +{ + return cpu->isa[thread->threadId()].flattenIntIndex(reg); +} + +template +int +O3ThreadContext::flattenFloatIndex(int reg) +{ + return cpu->isa[thread->threadId()].flattenFloatIndex(reg); +} + template void O3ThreadContext::setMiscRegNoEffect(int misc_reg, const MiscReg &val) -- cgit v1.2.3