From 3ad761bc8e89ff034fbf5ec6d8e9661e1025dcd7 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Sat, 30 Jun 2007 20:35:42 -0700 Subject: Make CPU models use new LoadLockedReq/StoreCondReq commands. --HG-- extra : convert_revision : ab78d9d1d88c3698edfd653d71c8882e1272b781 --- src/cpu/o3/lsq_unit.hh | 5 ++++- src/cpu/o3/lsq_unit_impl.hh | 4 +++- 2 files changed, 7 insertions(+), 2 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index d964b9f9f..be9224099 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -643,7 +643,10 @@ LSQUnit::read(Request *req, T &data, int load_idx) // if we the cache is not blocked, do cache access if (!lsq->cacheBlocked()) { PacketPtr data_pkt = - new Packet(req, MemCmd::ReadReq, Packet::Broadcast); + new Packet(req, + (req->isLocked() ? + MemCmd::LoadLockedReq : MemCmd::ReadReq), + Packet::Broadcast); data_pkt->dataStatic(load_inst->memData); LSQSenderState *state = new LSQSenderState; diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 810a6d29f..5ae1cc0e4 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -647,7 +647,9 @@ LSQUnit::writebackStores() memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); - MemCmd command = req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq; + MemCmd command = + req->isSwap() ? MemCmd::SwapReq : + (req->isLocked() ? MemCmd::WriteReq : MemCmd::StoreCondReq); PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast); data_pkt->dataStatic(inst->memData); -- cgit v1.2.3