From 3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98 Mon Sep 17 00:00:00 2001 From: Andreas Sandberg Date: Mon, 7 Jan 2013 13:05:35 -0500 Subject: arch: Make the ISA class inherit from SimObject The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU. --- src/cpu/o3/checker.cc | 1 + src/cpu/o3/cpu.cc | 12 ++++++++---- src/cpu/o3/cpu.hh | 2 +- src/cpu/o3/thread_context_impl.hh | 18 +++++++++--------- 4 files changed, 19 insertions(+), 14 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/checker.cc b/src/cpu/o3/checker.cc index c99428617..3ff3d86bc 100644 --- a/src/cpu/o3/checker.cc +++ b/src/cpu/o3/checker.cc @@ -82,6 +82,7 @@ O3CheckerParams::create() params->itb = itb; params->dtb = dtb; + params->isa = isa; params->system = system; params->cpu_id = cpu_id; params->profile = profile; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index c5421302d..9de1bf6b4 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -241,6 +241,8 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) TheISA::NumMiscRegs * numThreads, TheISA::ZeroReg), + isa(numThreads, NULL), + icachePort(&fetch, this), dcachePort(&iew.ldstQueue, this), @@ -340,6 +342,8 @@ FullO3CPU::FullO3CPU(DerivO3CPUParams *params) for (ThreadID tid = 0; tid < numThreads; tid++) { bool bindRegs = (tid <= active_threads - 1); + isa[tid] = params->isa[tid]; + commitRenameMap[tid].init(TheISA::NumIntRegs, params->numPhysIntRegs, lreg_idx, //Index for Logical. Regs @@ -1285,7 +1289,7 @@ template TheISA::MiscReg FullO3CPU::readMiscRegNoEffect(int misc_reg, ThreadID tid) { - return this->isa[tid].readMiscRegNoEffect(misc_reg); + return this->isa[tid]->readMiscRegNoEffect(misc_reg); } template @@ -1293,7 +1297,7 @@ TheISA::MiscReg FullO3CPU::readMiscReg(int misc_reg, ThreadID tid) { miscRegfileReads++; - return this->isa[tid].readMiscReg(misc_reg, tcBase(tid)); + return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid)); } template @@ -1301,7 +1305,7 @@ void FullO3CPU::setMiscRegNoEffect(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { - this->isa[tid].setMiscRegNoEffect(misc_reg, val); + this->isa[tid]->setMiscRegNoEffect(misc_reg, val); } template @@ -1310,7 +1314,7 @@ FullO3CPU::setMiscReg(int misc_reg, const TheISA::MiscReg &val, ThreadID tid) { miscRegfileWrites++; - this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid)); + this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid)); } template diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 1f9a8da6c..06e1ea336 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -634,7 +634,7 @@ class FullO3CPU : public BaseO3CPU /** Integer Register Scoreboard */ Scoreboard scoreboard; - TheISA::ISA isa[Impl::MaxThreads]; + std::vector isa; /** Instruction port. Note that it has to appear after the fetch stage. */ IcachePort icachePort; diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index 38e7c5dec..9d60a9700 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -219,14 +219,14 @@ template void O3ThreadContext::clearArchRegs() { - cpu->isa[thread->threadId()].clear(); + cpu->isa[thread->threadId()]->clear(); } template uint64_t O3ThreadContext::readIntReg(int reg_idx) { - reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); + reg_idx = cpu->isa[thread->threadId()]->flattenIntIndex(reg_idx); return cpu->readArchIntReg(reg_idx, thread->threadId()); } @@ -234,7 +234,7 @@ template TheISA::FloatReg O3ThreadContext::readFloatReg(int reg_idx) { - reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); + reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx); return cpu->readArchFloatReg(reg_idx, thread->threadId()); } @@ -242,7 +242,7 @@ template TheISA::FloatRegBits O3ThreadContext::readFloatRegBits(int reg_idx) { - reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); + reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx); return cpu->readArchFloatRegInt(reg_idx, thread->threadId()); } @@ -250,7 +250,7 @@ template void O3ThreadContext::setIntReg(int reg_idx, uint64_t val) { - reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx); + reg_idx = cpu->isa[thread->threadId()]->flattenIntIndex(reg_idx); cpu->setArchIntReg(reg_idx, val, thread->threadId()); conditionalSquash(); @@ -260,7 +260,7 @@ template void O3ThreadContext::setFloatReg(int reg_idx, FloatReg val) { - reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); + reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx); cpu->setArchFloatReg(reg_idx, val, thread->threadId()); conditionalSquash(); @@ -270,7 +270,7 @@ template void O3ThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val) { - reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx); + reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx); cpu->setArchFloatRegInt(reg_idx, val, thread->threadId()); conditionalSquash(); @@ -298,14 +298,14 @@ template int O3ThreadContext::flattenIntIndex(int reg) { - return cpu->isa[thread->threadId()].flattenIntIndex(reg); + return cpu->isa[thread->threadId()]->flattenIntIndex(reg); } template int O3ThreadContext::flattenFloatIndex(int reg) { - return cpu->isa[thread->threadId()].flattenFloatIndex(reg); + return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); } template -- cgit v1.2.3