From 537239b278f7b8171d2eb09ef7f99c332266c48f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Sun, 26 Aug 2007 20:24:18 -0700 Subject: Address Translation: Make SE mode use an actual TLB/MMU for translation like FS. --HG-- extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1 --- src/cpu/o3/O3CPU.py | 4 ++-- src/cpu/o3/alpha/cpu_builder.cc | 5 +++-- src/cpu/o3/alpha/params.hh | 2 -- src/cpu/o3/checker_builder.cc | 2 +- src/cpu/o3/cpu.cc | 2 -- src/cpu/o3/cpu.hh | 24 ------------------------ src/cpu/o3/fetch_impl.hh | 5 ----- src/cpu/o3/mips/params.hh | 13 +++++++------ src/cpu/o3/sparc/cpu_builder.cc | 5 +++-- src/cpu/o3/sparc/params.hh | 2 -- src/cpu/o3/thread_context.hh | 2 -- 11 files changed, 16 insertions(+), 50 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py index e691cfe5d..27ca8ce1e 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/O3CPU.py @@ -52,8 +52,8 @@ class DerivO3CPU(BaseCPU): else: checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True, warnOnlyOnLoadError=False), "checker") - checker.itb = Parent.itb - checker.dtb = Parent.dtb + checker.itb = Parent.itb + checker.dtb = Parent.dtb cachePorts = Param.Unsigned(200, "Cache Ports") icache_port = Port("Instruction Port") diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index 4db217abf..1aa3d1618 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -77,10 +77,11 @@ DerivO3CPUParams::create() params->cpu_id = cpu_id; params->activity = activity; -#if FULL_SYSTEM - params->system = system; params->itb = itb; params->dtb = dtb; + +#if FULL_SYSTEM + params->system = system; params->profile = profile; params->do_quiesce = do_quiesce; diff --git a/src/cpu/o3/alpha/params.hh b/src/cpu/o3/alpha/params.hh index b6b84b2a1..164c25312 100644 --- a/src/cpu/o3/alpha/params.hh +++ b/src/cpu/o3/alpha/params.hh @@ -54,10 +54,8 @@ class AlphaSimpleParams : public O3Params { public: -#if FULL_SYSTEM AlphaISA::ITB *itb; AlphaISA::DTB *dtb; -#endif }; #endif // __CPU_O3_ALPHA_PARAMS_HH__ diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc index 97425b08c..0799b9cb5 100644 --- a/src/cpu/o3/checker_builder.cc +++ b/src/cpu/o3/checker_builder.cc @@ -86,9 +86,9 @@ O3CheckerParams::create() params->progress_interval = 0; temp2++; -#if FULL_SYSTEM params->itb = itb; params->dtb = dtb; +#if FULL_SYSTEM params->system = system; params->cpu_id = cpu_id; params->profile = profile; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index cae6ae20c..98e200944 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -150,10 +150,8 @@ FullO3CPU::DeallocateContextEvent::description() template FullO3CPU::FullO3CPU(O3CPU *o3_cpu, Params *params) : BaseO3CPU(params), -#if FULL_SYSTEM itb(params->itb), dtb(params->dtb), -#endif tickEvent(this), removeInstsThisCycle(false), fetch(o3_cpu, params), diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 7d7e4e24d..d97a2080d 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -113,10 +113,8 @@ class FullO3CPU : public BaseO3CPU SwitchedOut }; -#if FULL_SYSTEM TheISA::ITB * itb; TheISA::DTB * dtb; -#endif /** Overall CPU status. */ Status _status; @@ -265,7 +263,6 @@ class FullO3CPU : public BaseO3CPU /** Registers statistics. */ void fullCPURegStats(); -#if FULL_SYSTEM /** Translates instruction requestion. */ Fault translateInstReq(RequestPtr &req, Thread *thread) { @@ -284,27 +281,6 @@ class FullO3CPU : public BaseO3CPU return this->dtb->translate(req, thread->getTC(), true); } -#else - /** Translates instruction requestion in syscall emulation mode. */ - Fault translateInstReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - - /** Translates data read request in syscall emulation mode. */ - Fault translateDataReadReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - - /** Translates data write request in syscall emulation mode. */ - Fault translateDataWriteReq(RequestPtr &req, Thread *thread) - { - return thread->getProcessPtr()->pTable->translate(req); - } - -#endif - /** Returns a specific port. */ Port *getPort(const std::string &if_name, int idx); diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 725baa1d0..043c65a4a 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1226,7 +1226,6 @@ DefaultFetch::fetch(bool &status_change) // Send the fault to commit. This thread will not do anything // until commit handles the fault. The only other way it can // wake up is if a squash comes along and changes the PC. -#if FULL_SYSTEM assert(numInst < fetchWidth); // Get a sequence number. inst_seq = cpu->getAndIncrementInstSeq(); @@ -1258,11 +1257,7 @@ DefaultFetch::fetch(bool &status_change) fetchStatus[tid] = TrapPending; status_change = true; -#else // !FULL_SYSTEM - fetchStatus[tid] = TrapPending; - status_change = true; -#endif // FULL_SYSTEM DPRINTF(Fetch, "[tid:%i]: fault (%s) detected @ PC %08p", tid, fault->name(), PC[tid]); } diff --git a/src/cpu/o3/mips/params.hh b/src/cpu/o3/mips/params.hh index d1ac62e21..2688d3fb3 100644 --- a/src/cpu/o3/mips/params.hh +++ b/src/cpu/o3/mips/params.hh @@ -36,8 +36,11 @@ #include "cpu/o3/params.hh" //Forward declarations -//class MipsDTB; -//class MipsITB; +namespace MipsISA +{ + class MipsDTB; + class MipsITB; +} class MemObject; class Process; class System; @@ -53,11 +56,9 @@ class MipsSimpleParams : public O3Params public: MipsSimpleParams() {} -#if FULL_SYSTEM //Full System Paramater Objects place here - MipsITB *itb; - MipsDTB *dtb; -#endif + MipsISA::ITB *itb; + MipsISA::DTB *dtb; }; #endif // __CPU_O3_MIPS_PARAMS_HH__ diff --git a/src/cpu/o3/sparc/cpu_builder.cc b/src/cpu/o3/sparc/cpu_builder.cc index 49f0f455d..b7c684431 100644 --- a/src/cpu/o3/sparc/cpu_builder.cc +++ b/src/cpu/o3/sparc/cpu_builder.cc @@ -78,10 +78,11 @@ DerivO3CPUParams::create() params->cpu_id = cpu_id; params->activity = activity; -#if FULL_SYSTEM - params->system = system; params->itb = itb; params->dtb = dtb; + +#if FULL_SYSTEM + params->system = system; params->profile = profile; params->do_quiesce = do_quiesce; diff --git a/src/cpu/o3/sparc/params.hh b/src/cpu/o3/sparc/params.hh index d399d64c4..09f523818 100644 --- a/src/cpu/o3/sparc/params.hh +++ b/src/cpu/o3/sparc/params.hh @@ -54,10 +54,8 @@ class SparcSimpleParams : public O3Params { public: -#if FULL_SYSTEM SparcISA::ITB *itb; SparcISA::DTB *dtb; -#endif }; #endif // __CPU_O3_SPARC_PARAMS_HH__ diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh index 93638673b..31e08db4c 100755 --- a/src/cpu/o3/thread_context.hh +++ b/src/cpu/o3/thread_context.hh @@ -66,13 +66,11 @@ class O3ThreadContext : public ThreadContext /** Pointer to the thread state that this TC corrseponds to. */ O3ThreadState *thread; -#if FULL_SYSTEM /** Returns a pointer to the ITB. */ TheISA::ITB *getITBPtr() { return cpu->itb; } /** Returns a pointer to the DTB. */ TheISA::DTB *getDTBPtr() { return cpu->dtb; } -#endif /** Returns a pointer to this CPU. */ virtual BaseCPU *getCpuPtr() { return cpu; } -- cgit v1.2.3