From c0f21b09c81e5562a916f7cb562a7df7f7709f4a Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Sat, 2 Dec 2006 13:33:46 -0500 Subject: Fixes for MIPS_SE compiling. Regressions seem to work, but Korey should make sure these changes (commit especially) work okay. src/cpu/o3/commit_impl.hh: src/cpu/o3/fetch_impl.hh: Fixes for MIPS_SE compile. --HG-- extra : convert_revision : fde9616f8e72b397c5ca965774172372cff53790 --- src/cpu/o3/commit_impl.hh | 1 + src/cpu/o3/fetch_impl.hh | 2 ++ 2 files changed, 3 insertions(+) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index e72679710..43305f962 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -748,6 +748,7 @@ DefaultCommit::commit() } } else { bdelay_done_seq_num = squashed_inst; + squash_bdelay_slot = true; } #endif diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 63d22b293..4c378e18b 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -1139,6 +1139,8 @@ DefaultFetch::fetch(bool &status_change) ext_inst = TheISA::makeExtMI(inst, fetch_PC); #elif THE_ISA == SPARC_ISA ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); +#elif THE_ISA == MIPS_ISA + ext_inst = TheISA::makeExtMI(inst, cpu->thread[tid]->getTC()); #endif // Create a new DynInst from the instruction fetched. -- cgit v1.2.3 From b618e733bd580391702a844404417f9723b94588 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 6 Dec 2006 14:23:31 -0500 Subject: Fix for MIPS_SE/m5.fast compile. --HG-- extra : convert_revision : dbb893250974ac6db7b6c1ba67263fd35098ca43 --- src/cpu/o3/commit_impl.hh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 43305f962..f400d757b 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -1197,16 +1197,16 @@ DefaultCommit::getInsts() rename_idx < fromRename->size; rename_idx++) { DynInstPtr inst = fromRename->insts[rename_idx]; - int tid = inst->threadNumber; if (!inst->isSquashed()) { DPRINTF(Commit, "Inserting PC %#x [sn:%i] [tid:%i] into ", - "skidBuffer.\n", inst->readPC(), inst->seqNum, tid); + "skidBuffer.\n", inst->readPC(), inst->seqNum, + inst->threadNumber); skidBuffer.push(inst); } else { DPRINTF(Commit, "Instruction PC %#x [sn:%i] [tid:%i] was " "squashed, skipping.\n", - inst->readPC(), inst->seqNum, tid); + inst->readPC(), inst->seqNum, inst->threadNumber); } } } -- cgit v1.2.3 From 1868c9fd7f9805e6f0a9cf3ceab958c8b36259b0 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 11 Dec 2006 23:47:30 -0500 Subject: Fix for fetch to use the icache's block size to generate proper access size. --HG-- extra : convert_revision : 0f292233ac05b584f527c32f80e3ca3d40a6a2c1 --- src/cpu/o3/fetch_impl.hh | 60 ++++++++++++++++++++++++------------------------ 1 file changed, 30 insertions(+), 30 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 4c378e18b..622259495 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -151,36 +151,6 @@ DefaultFetch::DefaultFetch(Params *params) " RoundRobin,LSQcount,IQcount}\n"); } - // Size of cache block. - cacheBlkSize = 64; - - // Create mask to get rid of offset bits. - cacheBlkMask = (cacheBlkSize - 1); - - for (int tid=0; tid < numThreads; tid++) { - - fetchStatus[tid] = Running; - - priorityList.push_back(tid); - - memReq[tid] = NULL; - - // Create space to store a cache line. - cacheData[tid] = new uint8_t[cacheBlkSize]; - cacheDataPC[tid] = 0; - cacheDataValid[tid] = false; - - delaySlotInfo[tid].branchSeqNum = -1; - delaySlotInfo[tid].numInsts = 0; - delaySlotInfo[tid].targetAddr = 0; - delaySlotInfo[tid].targetReady = false; - - stalls[tid].decode = false; - stalls[tid].rename = false; - stalls[tid].iew = false; - stalls[tid].commit = false; - } - // Get the size of an instruction. instSize = sizeof(TheISA::MachInst); } @@ -353,6 +323,36 @@ DefaultFetch::initStage() nextNPC[tid] = cpu->readNextNPC(tid); #endif } + + // Size of cache block. + cacheBlkSize = icachePort->peerBlockSize(); + + // Create mask to get rid of offset bits. + cacheBlkMask = (cacheBlkSize - 1); + + for (int tid=0; tid < numThreads; tid++) { + + fetchStatus[tid] = Running; + + priorityList.push_back(tid); + + memReq[tid] = NULL; + + // Create space to store a cache line. + cacheData[tid] = new uint8_t[cacheBlkSize]; + cacheDataPC[tid] = 0; + cacheDataValid[tid] = false; + + delaySlotInfo[tid].branchSeqNum = -1; + delaySlotInfo[tid].numInsts = 0; + delaySlotInfo[tid].targetAddr = 0; + delaySlotInfo[tid].targetReady = false; + + stalls[tid].decode = false; + stalls[tid].rename = false; + stalls[tid].iew = false; + stalls[tid].commit = false; + } } template -- cgit v1.2.3 From 34924ce3b82ec19322990c721369b08ddfd3df8a Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 11 Dec 2006 23:51:21 -0500 Subject: Fix up in case a req hasn't yet been generated for this instruction (if there was a fault prior to translation). --HG-- extra : convert_revision : 43f4ea5e6a234cc6071006eab72135c11b8523c8 --- src/cpu/o3/lsq_unit_impl.hh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 4facea9f9..3b84d3411 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -418,7 +418,8 @@ LSQUnit::executeLoad(DynInstPtr &inst) // realizes there is activity. // Mark it as executed unless it is an uncached load that // needs to hit the head of commit. - if (!(inst->req->isUncacheable()) || inst->isAtCommit()) { + if (!(inst->req && inst->req->isUncacheable()) || + inst->isAtCommit()) { inst->setExecuted(); } iewStage->instToCommit(inst); -- cgit v1.2.3 From 6c8c86f2f97913788237f763d4810ab12730ca60 Mon Sep 17 00:00:00 2001 From: Steve Reinhardt Date: Tue, 12 Dec 2006 09:58:40 -0800 Subject: Rename the StaticInst-based (read|set)(Int|Float)Reg methods to (read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version. --HG-- extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c --- src/cpu/o3/alpha/dyn_inst.hh | 35 +++++++++++++++++++---------------- src/cpu/o3/mips/dyn_inst.hh | 35 +++++++++++++++++++---------------- 2 files changed, 38 insertions(+), 32 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/alpha/dyn_inst.hh b/src/cpu/o3/alpha/dyn_inst.hh index 31df8ff78..49cc5a201 100644 --- a/src/cpu/o3/alpha/dyn_inst.hh +++ b/src/cpu/o3/alpha/dyn_inst.hh @@ -163,27 +163,28 @@ class AlphaDynInst : public BaseDynInst // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst *si, int idx) + uint64_t readIntRegOperand(const StaticInst *si, int idx) { return this->cpu->readIntReg(_srcRegIdx[idx]); } - FloatReg readFloatReg(const StaticInst *si, int idx, int width) + FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) { return this->cpu->readFloatReg(_srcRegIdx[idx], width); } - FloatReg readFloatReg(const StaticInst *si, int idx) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) { return this->cpu->readFloatReg(_srcRegIdx[idx]); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, + int width) { return this->cpu->readFloatRegBits(_srcRegIdx[idx], width); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { return this->cpu->readFloatRegBits(_srcRegIdx[idx]); } @@ -191,35 +192,37 @@ class AlphaDynInst : public BaseDynInst /** @todo: Make results into arrays so they can handle multiple dest * registers. */ - void setIntReg(const StaticInst *si, int idx, uint64_t val) + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) { this->cpu->setIntReg(_destRegIdx[idx], val); - BaseDynInst::setIntReg(si, idx, val); + BaseDynInst::setIntRegOperand(si, idx, val); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, + int width) { this->cpu->setFloatReg(_destRegIdx[idx], val, width); - BaseDynInst::setFloatReg(si, idx, val, width); + BaseDynInst::setFloatRegOperand(si, idx, val, width); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { this->cpu->setFloatReg(_destRegIdx[idx], val); - BaseDynInst::setFloatReg(si, idx, val); + BaseDynInst::setFloatRegOperand(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, - FloatRegBits val, int width) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val, int width) { this->cpu->setFloatRegBits(_destRegIdx[idx], val, width); - BaseDynInst::setFloatRegBits(si, idx, val); + BaseDynInst::setFloatRegOperandBits(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val) { this->cpu->setFloatRegBits(_destRegIdx[idx], val); - BaseDynInst::setFloatRegBits(si, idx, val); + BaseDynInst::setFloatRegOperandBits(si, idx, val); } /** Returns the physical register index of the i'th destination diff --git a/src/cpu/o3/mips/dyn_inst.hh b/src/cpu/o3/mips/dyn_inst.hh index 9e95b2bfb..833371e00 100755 --- a/src/cpu/o3/mips/dyn_inst.hh +++ b/src/cpu/o3/mips/dyn_inst.hh @@ -156,27 +156,28 @@ class MipsDynInst : public BaseDynInst // storage (which is pretty hard to imagine they would have reason // to do). - uint64_t readIntReg(const StaticInst *si, int idx) + uint64_t readIntRegOperand(const StaticInst *si, int idx) { return this->cpu->readIntReg(_srcRegIdx[idx]); } - FloatReg readFloatReg(const StaticInst *si, int idx, int width) + FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width) { return this->cpu->readFloatReg(_srcRegIdx[idx], width); } - FloatReg readFloatReg(const StaticInst *si, int idx) + FloatReg readFloatRegOperand(const StaticInst *si, int idx) { return this->cpu->readFloatReg(_srcRegIdx[idx]); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx, + int width) { return this->cpu->readFloatRegBits(_srcRegIdx[idx], width); } - FloatRegBits readFloatRegBits(const StaticInst *si, int idx) + FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) { return this->cpu->readFloatRegBits(_srcRegIdx[idx]); } @@ -184,35 +185,37 @@ class MipsDynInst : public BaseDynInst /** @todo: Make results into arrays so they can handle multiple dest * registers. */ - void setIntReg(const StaticInst *si, int idx, uint64_t val) + void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) { this->cpu->setIntReg(_destRegIdx[idx], val); - BaseDynInst::setIntReg(si, idx, val); + BaseDynInst::setIntRegOperand(si, idx, val); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val, + int width) { this->cpu->setFloatReg(_destRegIdx[idx], val, width); - BaseDynInst::setFloatReg(si, idx, val, width); + BaseDynInst::setFloatRegOperand(si, idx, val, width); } - void setFloatReg(const StaticInst *si, int idx, FloatReg val) + void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) { this->cpu->setFloatReg(_destRegIdx[idx], val); - BaseDynInst::setFloatReg(si, idx, val); + BaseDynInst::setFloatRegOperand(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, - FloatRegBits val, int width) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val, int width) { this->cpu->setFloatRegBits(_destRegIdx[idx], val, width); - BaseDynInst::setFloatRegBits(si, idx, val); + BaseDynInst::setFloatRegOperandBits(si, idx, val); } - void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val) + void setFloatRegOperandBits(const StaticInst *si, int idx, + FloatRegBits val) { this->cpu->setFloatRegBits(_destRegIdx[idx], val); - BaseDynInst::setFloatRegBits(si, idx, val); + BaseDynInst::setFloatRegOperandBits(si, idx, val); } /** Returns the physical register index of the i'th destination -- cgit v1.2.3