From 7d0344704a9ecc566d82ad43ec44b4becbaf4d77 Mon Sep 17 00:00:00 2001
From: Ali Saidi <Ali.Saidi@ARM.com>
Date: Fri, 24 Jan 2014 15:29:30 -0600
Subject: arch, cpu: Add support for flattening misc register indexes.

With ARMv8 support the same misc register id  results in accessing different
registers depending on the current mode of the processor. This patch adds
the same orthogonality to the misc register file as the others (int, float, cc).
For all the othre ISAs this is currently a null-implementation.

Additionally, a system variable is added to all the ISA objects.
---
 src/cpu/o3/thread_context.hh      | 1 +
 src/cpu/o3/thread_context_impl.hh | 7 +++++++
 2 files changed, 8 insertions(+)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 88cf75f4f..27f8e9561 100755
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -244,6 +244,7 @@ class O3ThreadContext : public ThreadContext
     virtual int flattenIntIndex(int reg);
     virtual int flattenFloatIndex(int reg);
     virtual int flattenCCIndex(int reg);
+    virtual int flattenMiscIndex(int reg);
 
     /** Returns the number of consecutive store conditional failures. */
     // @todo: Figure out where these store cond failures should go.
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index c818260f4..43e903135 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -291,6 +291,13 @@ O3ThreadContext<Impl>::flattenCCIndex(int reg)
     return cpu->isa[thread->threadId()]->flattenCCIndex(reg);
 }
 
+template <class Impl>
+int
+O3ThreadContext<Impl>::flattenMiscIndex(int reg)
+{
+    return cpu->isa[thread->threadId()]->flattenMiscIndex(reg);
+}
+
 template <class Impl>
 void
 O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
-- 
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