From aa8c6e9c959eab4d516bc07593bea20ade9ad80c Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Fri, 13 Aug 2010 06:16:02 -0700
Subject: CPU: Add readBytes and writeBytes functions to the exec contexts.

---
 src/cpu/o3/cpu.hh      |  6 ++----
 src/cpu/o3/lsq.hh      | 12 ++++--------
 src/cpu/o3/lsq_unit.hh | 27 ++++++++++++---------------
 3 files changed, 18 insertions(+), 27 deletions(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 82d4ca25b..a102a21f5 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -702,18 +702,16 @@ class FullO3CPU : public BaseO3CPU
     std::vector<ThreadID> tids;
 
     /** CPU read function, forwards read to LSQ. */
-    template <class T>
     Fault read(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
-               T &data, int load_idx)
+               uint8_t *data, int load_idx)
     {
         return this->iew.ldstQueue.read(req, sreqLow, sreqHigh,
                                         data, load_idx);
     }
 
     /** CPU write function, forwards write to LSQ. */
-    template <class T>
     Fault write(RequestPtr &req, RequestPtr &sreqLow, RequestPtr &sreqHigh,
-                T &data, int store_idx)
+                uint8_t *data, int store_idx)
     {
         return this->iew.ldstQueue.write(req, sreqLow, sreqHigh,
                                          data, store_idx);
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 7a7ea917f..0ad5d51c2 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -273,16 +273,14 @@ class LSQ {
     /** Executes a read operation, using the load specified at the load
      * index.
      */
-    template <class T>
     Fault read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
-               T &data, int load_idx);
+               uint8_t *data, int load_idx);
 
     /** Executes a store operation, using the store specified at the store
      * index.
      */
-    template <class T>
     Fault write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
-                T &data, int store_idx);
+                uint8_t *data, int store_idx);
 
     /** The CPU pointer. */
     O3CPU *cpu;
@@ -371,10 +369,9 @@ class LSQ {
 };
 
 template <class Impl>
-template <class T>
 Fault
 LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
-                T &data, int load_idx)
+                uint8_t *data, int load_idx)
 {
     ThreadID tid = req->threadId();
 
@@ -382,10 +379,9 @@ LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
 }
 
 template <class Impl>
-template <class T>
 Fault
 LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
-                 T &data, int store_idx)
+                 uint8_t *data, int store_idx)
 {
     ThreadID tid = req->threadId();
 
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index c19a368d1..10b1ed11a 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -474,14 +474,12 @@ class LSQUnit {
 
   public:
     /** Executes the load at the given index. */
-    template <class T>
-    Fault read(Request *req, Request *sreqLow, Request *sreqHigh, T &data,
-               int load_idx);
+    Fault read(Request *req, Request *sreqLow, Request *sreqHigh,
+               uint8_t *data, int load_idx);
 
     /** Executes the store at the given index. */
-    template <class T>
-    Fault write(Request *req, Request *sreqLow, Request *sreqHigh, T &data,
-                int store_idx);
+    Fault write(Request *req, Request *sreqLow, Request *sreqHigh,
+                uint8_t *data, int store_idx);
 
     /** Returns the index of the head load instruction. */
     int getLoadHead() { return loadHead; }
@@ -514,10 +512,9 @@ class LSQUnit {
 };
 
 template <class Impl>
-template <class T>
 Fault
 LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
-                    T &data, int load_idx)
+                    uint8_t *data, int load_idx)
 {
     DynInstPtr load_inst = loadQueue[load_idx];
 
@@ -605,7 +602,8 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
             // Get shift amount for offset into the store's data.
             int shift_amt = req->getVaddr() & (store_size - 1);
 
-            memcpy(&data, storeQueue[store_idx].data + shift_amt, sizeof(T));
+            memcpy(data, storeQueue[store_idx].data + shift_amt,
+                   req->getSize());
 
             assert(!load_inst->memData);
             load_inst->memData = new uint8_t[64];
@@ -809,10 +807,9 @@ LSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh,
 }
 
 template <class Impl>
-template <class T>
 Fault
 LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
-                     T &data, int store_idx)
+                     uint8_t *data, int store_idx)
 {
     assert(storeQueue[store_idx].inst);
 
@@ -824,17 +821,17 @@ LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
     storeQueue[store_idx].req = req;
     storeQueue[store_idx].sreqLow = sreqLow;
     storeQueue[store_idx].sreqHigh = sreqHigh;
-    storeQueue[store_idx].size = sizeof(T);
+    unsigned size = req->getSize();
+    storeQueue[store_idx].size = size;
+    assert(size <= sizeof(storeQueue[store_idx].data));
 
     // Split stores can only occur in ISAs with unaligned memory accesses.  If
     // a store request has been split, sreqLow and sreqHigh will be non-null.
     if (TheISA::HasUnalignedMemAcc && sreqLow) {
         storeQueue[store_idx].isSplit = true;
     }
-    assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
 
-    T gData = htog(data);
-    memcpy(storeQueue[store_idx].data, &gData, sizeof(T));
+    memcpy(storeQueue[store_idx].data, data, size);
 
     // This function only writes the data to the store queue, so no fault
     // can happen here.
-- 
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