From b13a79ee717b876e4bc837ba95985abd4d18162f Mon Sep 17 00:00:00 2001 From: Matt Horsnell Date: Tue, 18 Jan 2011 16:30:05 -0600 Subject: O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA. --- src/cpu/o3/fetch_impl.hh | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) (limited to 'src/cpu/o3') diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 736a66c64..927af42c3 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -384,7 +384,7 @@ DefaultFetch::processCacheCompletion(PacketPtr pkt) { ThreadID tid = pkt->req->threadId(); - DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid); + DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); assert(!pkt->wasNacked()); @@ -1011,7 +1011,7 @@ DefaultFetch::buildInst(ThreadID tid, StaticInstPtr staticInst, instruction->setThreadState(cpu->thread[tid]); DPRINTF(Fetch, "[tid:%i]: Instruction PC %#x (%d) created " - "[sn:%lli]\n", tid, thisPC.instAddr(), + "[sn:%lli].\n", tid, thisPC.instAddr(), thisPC.microPC(), seq); DPRINTF(Fetch, "[tid:%i]: Instruction is: %s\n", tid, @@ -1180,7 +1180,6 @@ DefaultFetch::fetch(bool &status_change) ExtMachInst extMachInst; extMachInst = predecoder.getExtMachInst(thisPC); - pcOffset = 0; staticInst = StaticInstPtr(extMachInst, thisPC.instAddr()); @@ -1188,7 +1187,12 @@ DefaultFetch::fetch(bool &status_change) ++fetchedInsts; if (staticInst->isMacroop()) + { curMacroop = staticInst; + } + else { + pcOffset = 0; + } } else { // We need more bytes for this instruction. break; @@ -1196,8 +1200,10 @@ DefaultFetch::fetch(bool &status_change) } if (curMacroop) { staticInst = curMacroop->fetchMicroop(thisPC.microPC()); - if (staticInst->isLastMicroop()) + if (staticInst->isLastMicroop()) { curMacroop = NULL; + pcOffset = 0; + } } DynInstPtr instruction = -- cgit v1.2.3