From bd6f2bb538b09ce221c46d1ec5d5bfbf9a1d3350 Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Sun, 19 Apr 2009 21:44:15 -0700
Subject: Mem: Change isLlsc to isLLSC.

---
 src/cpu/o3/lsq_unit.hh      | 4 ++--
 src/cpu/o3/lsq_unit_impl.hh | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index 9f0f38f06..28e6f4506 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -514,7 +514,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
             "storeHead: %i addr: %#x\n",
             load_idx, store_idx, storeHead, req->getPaddr());
 
-    if (req->isLlsc()) {
+    if (req->isLLSC()) {
         // Disable recording the result temporarily.  Writing to misc
         // regs normally updates the result, but this is not the
         // desired behavior when handling store conditionals.
@@ -647,7 +647,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
     if (!lsq->cacheBlocked()) {
         PacketPtr data_pkt =
             new Packet(req,
-                       (req->isLlsc() ?
+                       (req->isLLSC() ?
                         MemCmd::LoadLockedReq : MemCmd::ReadReq),
                        Packet::Broadcast);
         data_pkt->dataStatic(load_inst->memData);
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index f5753a4ef..afc9faf9c 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -652,7 +652,7 @@ LSQUnit<Impl>::writebackStores()
 
         MemCmd command =
             req->isSwap() ? MemCmd::SwapReq :
-            (req->isLlsc() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
+            (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
         PacketPtr data_pkt = new Packet(req, command,
                                         Packet::Broadcast);
         data_pkt->dataStatic(inst->memData);
-- 
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