From be28d96510e0e722db83b26f1a12d3f5de979b32 Mon Sep 17 00:00:00 2001
From: Andreas Sandberg <andreas.sandberg@arm.com>
Date: Wed, 6 Apr 2016 19:43:31 +0100
Subject: Revert power patch sets with unexpected interactions

The following patches had unexpected interactions with the current
upstream code and have been reverted for now:

e07fd01651f3: power: Add support for power models
831c7f2f9e39: power: Low-power idle power state for idle CPUs
4f749e00b667: power: Add power states to ClockedObject

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>

--HG--
extra : amend_source : 0b6fb073c6bbc24be533ec431eb51fbf1b269508
---
 src/cpu/o3/cpu.cc        | 4 ----
 src/cpu/o3/fetch_impl.hh | 6 +++---
 src/cpu/o3/lsq.hh        | 4 ++--
 src/cpu/o3/lsq_impl.hh   | 3 +--
 4 files changed, 6 insertions(+), 11 deletions(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 73174e4a9..79ad705bf 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -735,8 +735,6 @@ FullO3CPU<Impl>::activateContext(ThreadID tid)
         lastActivatedCycle = curTick();
 
         _status = Running;
-
-        BaseCPU::activateContext(tid);
     }
 }
 
@@ -757,8 +755,6 @@ FullO3CPU<Impl>::suspendContext(ThreadID tid)
     }
 
     DPRINTF(Quiesce, "Suspending Context\n");
-
-    BaseCPU::suspendContext(tid);
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 3b29d87d4..4b1479bcb 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -378,7 +378,7 @@ template<class Impl>
 void
 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
 {
-    ThreadID tid = cpu->contextToThread(pkt->req->contextId());
+    ThreadID tid = pkt->req->threadId();
 
     DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
     assert(!cpu->switchedOut());
@@ -622,7 +622,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
     RequestPtr mem_req =
         new Request(tid, fetchBufferBlockPC, fetchBufferSize,
                     Request::INST_FETCH, cpu->instMasterId(), pc,
-                    cpu->thread[tid]->contextId());
+                    cpu->thread[tid]->contextId(), tid);
 
     mem_req->taskId(cpu->taskId());
 
@@ -640,7 +640,7 @@ template <class Impl>
 void
 DefaultFetch<Impl>::finishTranslation(const Fault &fault, RequestPtr mem_req)
 {
-    ThreadID tid = cpu->contextToThread(mem_req->contextId());
+    ThreadID tid = mem_req->threadId();
     Addr fetchBufferBlockPC = mem_req->getVaddr();
 
     assert(!cpu->switchedOut());
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index 6bc9b3d73..dcd676221 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -334,7 +334,7 @@ Fault
 LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
                 int load_idx)
 {
-    ThreadID tid = cpu->contextToThread(req->contextId());
+    ThreadID tid = req->threadId();
 
     return thread[tid].read(req, sreqLow, sreqHigh, load_idx);
 }
@@ -344,7 +344,7 @@ Fault
 LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
                  uint8_t *data, int store_idx)
 {
-    ThreadID tid = cpu->contextToThread(req->contextId());
+    ThreadID tid = req->threadId();
 
     return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
 }
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 9080907fe..06467243d 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -347,8 +347,7 @@ LSQ<Impl>::recvTimingResp(PacketPtr pkt)
         DPRINTF(LSQ, "Got error packet back for address: %#X\n",
                 pkt->getAddr());
 
-    thread[cpu->contextToThread(pkt->req->contextId())]
-        .completeDataAccess(pkt);
+    thread[pkt->req->threadId()].completeDataAccess(pkt);
 
     if (pkt->isInvalidate()) {
         // This response also contains an invalidate; e.g. this can be the case
-- 
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