From c75ff71139d6358678835cca63e35d1135eaf466 Mon Sep 17 00:00:00 2001
From: Mitch Hayenga <mitch.hayenga@arm.com>
Date: Thu, 7 Apr 2016 09:30:20 -0500
Subject: mem: Remove threadId from memory request class

In general, the ThreadID parameter is unnecessary in the memory system
as the ContextID is what is used for the purposes of locks/wakeups.
Since we allocate sequential ContextIDs for each thread on MT-enabled
CPUs, ThreadID is unnecessary as the CPUs can identify the requesting
thread through sideband info (SenderState / LSQ entries) or ContextID
offset from the base ContextID for a cpu.

This is a re-spin of 20264eb after the revert (bd1c6789) and includes
some fixes of that commit.
---
 src/cpu/o3/fetch_impl.hh | 6 +++---
 src/cpu/o3/lsq.hh        | 4 ++--
 src/cpu/o3/lsq_impl.hh   | 3 ++-
 3 files changed, 7 insertions(+), 6 deletions(-)

(limited to 'src/cpu/o3')

diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 4b1479bcb..3b29d87d4 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -378,7 +378,7 @@ template<class Impl>
 void
 DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
 {
-    ThreadID tid = pkt->req->threadId();
+    ThreadID tid = cpu->contextToThread(pkt->req->contextId());
 
     DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid);
     assert(!cpu->switchedOut());
@@ -622,7 +622,7 @@ DefaultFetch<Impl>::fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc)
     RequestPtr mem_req =
         new Request(tid, fetchBufferBlockPC, fetchBufferSize,
                     Request::INST_FETCH, cpu->instMasterId(), pc,
-                    cpu->thread[tid]->contextId(), tid);
+                    cpu->thread[tid]->contextId());
 
     mem_req->taskId(cpu->taskId());
 
@@ -640,7 +640,7 @@ template <class Impl>
 void
 DefaultFetch<Impl>::finishTranslation(const Fault &fault, RequestPtr mem_req)
 {
-    ThreadID tid = mem_req->threadId();
+    ThreadID tid = cpu->contextToThread(mem_req->contextId());
     Addr fetchBufferBlockPC = mem_req->getVaddr();
 
     assert(!cpu->switchedOut());
diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
index dcd676221..6bc9b3d73 100644
--- a/src/cpu/o3/lsq.hh
+++ b/src/cpu/o3/lsq.hh
@@ -334,7 +334,7 @@ Fault
 LSQ<Impl>::read(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
                 int load_idx)
 {
-    ThreadID tid = req->threadId();
+    ThreadID tid = cpu->contextToThread(req->contextId());
 
     return thread[tid].read(req, sreqLow, sreqHigh, load_idx);
 }
@@ -344,7 +344,7 @@ Fault
 LSQ<Impl>::write(RequestPtr req, RequestPtr sreqLow, RequestPtr sreqHigh,
                  uint8_t *data, int store_idx)
 {
-    ThreadID tid = req->threadId();
+    ThreadID tid = cpu->contextToThread(req->contextId());
 
     return thread[tid].write(req, sreqLow, sreqHigh, data, store_idx);
 }
diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh
index 06467243d..9080907fe 100644
--- a/src/cpu/o3/lsq_impl.hh
+++ b/src/cpu/o3/lsq_impl.hh
@@ -347,7 +347,8 @@ LSQ<Impl>::recvTimingResp(PacketPtr pkt)
         DPRINTF(LSQ, "Got error packet back for address: %#X\n",
                 pkt->getAddr());
 
-    thread[pkt->req->threadId()].completeDataAccess(pkt);
+    thread[cpu->contextToThread(pkt->req->contextId())]
+        .completeDataAccess(pkt);
 
     if (pkt->isInvalidate()) {
         // This response also contains an invalidate; e.g. this can be the case
-- 
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